From: Vidya Sagar <vidyas@nvidia.com>
To: <bhelgaas@google.com>, <lorenzo.pieralisi@arm.com>,
<robh+dt@kernel.org>, <thierry.reding@gmail.com>,
<jonathanh@nvidia.com>
Cc: <kishon@ti.com>, <vkoul@kernel.org>, <kw@linux.com>,
<krzysztof.kozlowski@canonical.com>, <p.zabel@pengutronix.de>,
<mperttunen@nvidia.com>, <linux-pci@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-phy@lists.infradead.org>,
<kthota@nvidia.com>, <mmaddireddy@nvidia.com>,
<vidyas@nvidia.com>, <sagar.tv@gmail.com>
Subject: [PATCH V1 03/10] dt-bindings: memory: Add Tegra234 PCIe memory
Date: Sat, 5 Feb 2022 21:51:37 +0530 [thread overview]
Message-ID: <20220205162144.30240-4-vidyas@nvidia.com> (raw)
In-Reply-To: <20220205162144.30240-1-vidyas@nvidia.com>
Add the memory client and stream ID definitions for the PCIe hardware
found on Tegra234 SoCs.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
include/dt-bindings/memory/tegra234-mc.h | 64 ++++++++++++++++++++++++
1 file changed, 64 insertions(+)
diff --git a/include/dt-bindings/memory/tegra234-mc.h b/include/dt-bindings/memory/tegra234-mc.h
index 2662f70c15c6..60017684858a 100644
--- a/include/dt-bindings/memory/tegra234-mc.h
+++ b/include/dt-bindings/memory/tegra234-mc.h
@@ -7,15 +7,53 @@
#define TEGRA234_SID_INVALID 0x00
#define TEGRA234_SID_PASSTHROUGH 0x7f
+/* NISO0 stream IDs */
+#define TEGRA234_SID_PCIE0 0x12U
+#define TEGRA234_SID_PCIE4 0x13U
+#define TEGRA234_SID_PCIE5 0x14U
+#define TEGRA234_SID_PCIE6 0x15U
+#define TEGRA234_SID_PCIE9 0x1FU
/* NISO1 stream IDs */
#define TEGRA234_SID_SDMMC4 0x02
+#define TEGRA234_SID_PCIE1 0x5U
+#define TEGRA234_SID_PCIE2 0x6U
+#define TEGRA234_SID_PCIE3 0x7U
+#define TEGRA234_SID_PCIE7 0x8U
+#define TEGRA234_SID_PCIE8 0x9U
+#define TEGRA234_SID_PCIE10 0xBU
#define TEGRA234_SID_BPMP 0x10
/*
* memory client IDs
*/
+/* PCIE6 read clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28
+/* PCIE6 write clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE6AW 0x29
+/* PCIE7 read clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE7AR 0x2a
+/* PCIE7 write clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE7AW 0x30
+/* PCIE8 read clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE8AR 0x32
+/* PCIE8 write clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE8AW 0x3b
+/* PCIE9 read clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE9AR 0x3c
+/* PCIE6r1 read clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE6AR1 0x3d
+/* PCIE9 write clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE9AW 0x3e
+/* PCIE10 read clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE10AR 0x3f
+/* PCIE10 write clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE10AW 0x40
+/* PCIE10r1 read clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48
+/* PCIE7r1 read clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49
/* sdmmcd memory read client */
#define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63
/* sdmmcd memory write client */
@@ -28,5 +66,31 @@
#define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95
/* BPMPDMA write client */
#define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96
+/* PCIE0 read clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE0R 0xd8
+/* PCIE0 write clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE0W 0xd9
+/* PCIE1 read clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE1R 0xda
+/* PCIE1 write clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE1W 0xdb
+/* PCIE2 read clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE2AR 0xdc
+/* PCIE2 write clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE2AW 0xdd
+/* PCIE3 read clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE3R 0xde
+/* PCIE3 write clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE3W 0xdf
+/* PCIE4 read clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE4R 0xe0
+/* PCIE4 write clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE4W 0xe1
+/* PCIE5 read clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE5R 0xe2
+/* PCIE5 write clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE5W 0xe3
+/* PCIE5r1 read clients */
+#define TEGRA234_MEMORY_CLIENT_PCIE5R1 0xef
#endif
--
2.17.1
next prev parent reply other threads:[~2022-02-05 16:22 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-05 16:21 [PATCH V1 00/10] PCI: tegra: Add Tegra234 PCIe support Vidya Sagar
2022-02-05 16:21 ` [PATCH V1 01/10] dt-bindings: Add Tegra234 PCIe clocks and resets Vidya Sagar
2022-02-11 14:51 ` Rob Herring
2022-02-05 16:21 ` [PATCH V1 02/10] dt-bindings: power: Add Tegra234 PCIe power domains Vidya Sagar
2022-02-11 14:52 ` Rob Herring
2022-02-05 16:21 ` Vidya Sagar [this message]
2022-02-06 11:33 ` [PATCH V1 03/10] dt-bindings: memory: Add Tegra234 PCIe memory Krzysztof Kozlowski
2022-02-24 19:04 ` Thierry Reding
2022-02-11 14:53 ` Rob Herring
2022-02-05 16:21 ` [PATCH V1 04/10] dt-bindings: PHY: P2U: Add support for Tegra234 P2U block Vidya Sagar
2022-02-07 6:47 ` Raul Tambre
2022-02-11 14:55 ` Rob Herring
2022-02-05 16:21 ` [PATCH V1 05/10] dt-bindings: PCI: tegra: Add device tree support for Tegra234 Vidya Sagar
2022-02-11 14:57 ` Rob Herring
2022-02-05 16:21 ` [PATCH V1 06/10] arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT Vidya Sagar
2022-02-05 16:21 ` [PATCH V1 07/10] arm64: tegra: Enable PCIe slots in P3737-0000 board Vidya Sagar
2022-02-06 11:29 ` Krzysztof Kozlowski
2022-02-05 16:21 ` [PATCH V1 08/10] phy: tegra: Add PCIe PIPE2UPHY support for Tegra234 Vidya Sagar
2022-02-05 16:21 ` [PATCH V1 09/10] PCI: Disable MSI for Tegra234 root ports Vidya Sagar
2022-02-07 17:36 ` Bjorn Helgaas
2022-04-23 7:22 ` Vidya Sagar
2022-02-05 16:21 ` [PATCH V1 10/10] PCI: tegra: Add Tegra234 PCIe support Vidya Sagar
2022-02-07 18:19 ` Bjorn Helgaas
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