From: "David E. Box" <david.e.box@linux.intel.com>
To: hdegoede@redhat.com, david.e.box@linux.intel.com,
mgross@linux.intel.com, rjw@rjwysocki.net,
srinivas.pandruvada@intel.com
Cc: linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org
Subject: [PATCH 3/3] platform/x86/intel: vsec: Add DG2 support
Date: Mon, 14 Feb 2022 13:32:58 -0800 [thread overview]
Message-ID: <20220214213258.1929462-4-david.e.box@linux.intel.com> (raw)
In-Reply-To: <20220214213258.1929462-1-david.e.box@linux.intel.com>
Add Platform Monitoring Technology support for DG2 platforms.
Signed-off-by: David E. Box <david.e.box@linux.intel.com>
---
drivers/platform/x86/intel/pmt/class.c | 2 ++
drivers/platform/x86/intel/vsec.c | 9 +++++++++
2 files changed, 11 insertions(+)
diff --git a/drivers/platform/x86/intel/pmt/class.c b/drivers/platform/x86/intel/pmt/class.c
index a3ec09fe2f38..d25fffb2103d 100644
--- a/drivers/platform/x86/intel/pmt/class.c
+++ b/drivers/platform/x86/intel/pmt/class.c
@@ -31,6 +31,8 @@
static const struct pci_device_id pmt_telem_early_client_pci_ids[] = {
{ PCI_VDEVICE(INTEL, 0x467d) }, /* ADL */
{ PCI_VDEVICE(INTEL, 0x490e) }, /* DG1 */
+ { PCI_VDEVICE(INTEL, 0x4f93) }, /* DG2_G10 */
+ { PCI_VDEVICE(INTEL, 0x4f95) }, /* DG2_G11 */
{ PCI_VDEVICE(INTEL, 0x9a0d) }, /* TGL */
{ }
};
diff --git a/drivers/platform/x86/intel/vsec.c b/drivers/platform/x86/intel/vsec.c
index d182122c261d..f256c7ca5452 100644
--- a/drivers/platform/x86/intel/vsec.c
+++ b/drivers/platform/x86/intel/vsec.c
@@ -396,17 +396,26 @@ static const struct intel_vsec_platform_info dg1_info = {
.quirks = VSEC_QUIRK_NO_DVSEC,
};
+/* DG2 info */
+static const struct intel_vsec_platform_info dg2_info = {
+ .quirks = VSEC_QUIRK_TABLE_SHIFT
+};
+
#ifdef CONFIG_PM_SLEEP
static const struct dev_pm_ops intel_vsec_pm_ops = {};
#endif
#define PCI_DEVICE_ID_INTEL_VSEC_ADL 0x467d
#define PCI_DEVICE_ID_INTEL_VSEC_DG1 0x490e
+#define PCI_DEVICE_ID_INTEL_VSEC_DG2_G10 0x4f93
+#define PCI_DEVICE_ID_INTEL_VSEC_DG2_G11 0x4f95
#define PCI_DEVICE_ID_INTEL_VSEC_OOBMSM 0x09a7
#define PCI_DEVICE_ID_INTEL_VSEC_TGL 0x9a0d
static const struct pci_device_id intel_vsec_pci_ids[] = {
{ PCI_DEVICE_DATA(INTEL, VSEC_ADL, &tgl_info) },
{ PCI_DEVICE_DATA(INTEL, VSEC_DG1, &dg1_info) },
+ { PCI_DEVICE_DATA(INTEL, VSEC_DG2_G10, &dg2_info) },
+ { PCI_DEVICE_DATA(INTEL, VSEC_DG2_G11, &dg2_info) },
{ PCI_DEVICE_DATA(INTEL, VSEC_OOBMSM, NULL) },
{ PCI_DEVICE_DATA(INTEL, VSEC_TGL, &tgl_info) },
{ }
--
2.25.1
prev parent reply other threads:[~2022-02-14 21:35 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-14 21:32 [PATCH 0/3] Add pm_runtime and DG2 support David E. Box
2022-02-14 21:32 ` [PATCH 1/3] platform/x86/intel: pmt: Remove bin_attribute mmap support to runtime pm David E. Box
2022-02-21 9:05 ` Hans de Goede
2022-02-21 17:06 ` David E. Box
2022-02-14 21:32 ` [PATCH 2/3] platform/x86/intel: vsec: Enable runtime D3 David E. Box
2022-02-14 21:32 ` David E. Box [this message]
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