Re: [PATCH v9 00/17] Introduce Architectural LBR for vPMU

Yang, Weijiang
2022-02-21T06:11:50Z

Ping...

Hi, Paolo and other maintainers,

Arch LBR is the enhancement and replacement of Legacy LBR, this
patch-set is

the necessity for guest Arch LBR usage on new Intel platforms starting from

Sapphire Rapids.

We're appreciated for your review and comments on these patches, thanks
a lot!

On 2/16/2022 5:25 AM, Yang Weijiang wrote:
> The Architectural Last Branch Records (LBRs) is published in release
> Intel Architecture Instruction Set Extensions and Future Features
> Programming Reference[0].
>
> The main advantages of Arch LBR are [1]:
> - Faster context switching due to XSAVES support and faster reset of
> LBR MSRs via the new DEPTH MSR
> - Faster LBR read for a non-PEBS event due to XSAVES support, which
> lowers the overhead of the NMI handler.
> - Linux kernel can support the LBR features without knowing the model
> number of the current CPU.
>
> From end user's point of view, the usage of Arch LBR is the same as
> the Legacy LBR that has been merged in the mainline.
>
> Note, In this KVM series, we impose one restriction for guest Arch LBR:
> Guest can only set the same LBR record depth as host, this is due to
> the special behavior of MSR_ARCH_LBR_DEPTH: 1) On write to the MSR,
> it'll reset all Arch LBR recording MSRs to 0s. 2) XRSTORS resets all
> record MSRs to 0s if the saved depth mismatches MSR_ARCH_LBR_DEPTH.
>
> But this restriction won't impact guest perf tool usage.
>
> [0]https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
> [1]https://lore.kernel.org/lkml/1593780569-62993-1-git-send-email-kan.liang@linux.intel.com/
>
> Qemu patch:
> https://patchwork.ozlabs.org/project/qemu-devel/cover/20220215195258.29149-1-weijiang.yang@intel.com/
>
> Previous version:
> v8:https://lkml.kernel.org/kvm/1629791777-16430-1-git-send-email-weijiang.yang@intel.com/
>
> Changes in v9:
> 1. Added Arch LBR MSR access interface for userspace.
> 2. Refactored XSS related dependent patches so that xsaves/xrstors can work for guest.
> 3. Refactored Arch LBR CTL and DEPTH MSR handling in KVM.
> 4. Rebased and tested on kernel base-commit: c5d9ae265b10
>
> Like Xu (6):
> perf/x86/intel: Fix the comment about guest LBR support on KVM
> perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers
> KVM: vmx/pmu: Emulate MSR_ARCH_LBR_DEPTH for guest Arch LBR
> KVM: vmx/pmu: Emulate MSR_ARCH_LBR_CTL for guest Arch LBR
> KVM: x86: Refine the matching and clearing logic for supported_xss
> KVM: x86: Add XSAVE Support for Architectural LBR
>
> Sean Christopherson (2):
> KVM: x86: Report XSS as an MSR to be saved if there are supported
> features
> KVM: x86: Load guest fpu state when accessing MSRs managed by XSAVES
>
> Yang Weijiang (9):
> KVM: x86: Refresh CPUID on writes to MSR_IA32_XSS
> KVM: x86: Add Arch LBR MSRs to msrs_to_save_all list
> KVM: x86/pmu: Refactor code to support guest Arch LBR
> KVM: x86/vmx: Check Arch LBR config when return perf capabilities
> KVM: nVMX: Add necessary Arch LBR settings for nested VM
> KVM: x86/vmx: Clear Arch LBREn bit before inject #DB to guest
> KVM: x86/vmx: Flip Arch LBREn bit on guest state change
> KVM: x86: Add Arch LBR MSR access interface
> KVM: x86/cpuid: Advertise Arch LBR feature in CPUID
>
> arch/x86/events/intel/core.c | 3 +-
> arch/x86/events/intel/lbr.c | 6 +-
> arch/x86/include/asm/kvm_host.h | 7 ++
> arch/x86/include/asm/msr-index.h | 1 +
> arch/x86/include/asm/vmx.h | 4 +
> arch/x86/kvm/cpuid.c | 54 ++++++++++-
> arch/x86/kvm/vmx/capabilities.h | 8 ++
> arch/x86/kvm/vmx/nested.c | 7 +-
> arch/x86/kvm/vmx/pmu_intel.c | 155 ++++++++++++++++++++++++++++---
> arch/x86/kvm/vmx/vmcs12.c | 1 +
> arch/x86/kvm/vmx/vmcs12.h | 3 +-
> arch/x86/kvm/vmx/vmx.c | 65 ++++++++++++-
> arch/x86/kvm/x86.c | 78 +++++++++++++++-
> 13 files changed, 356 insertions(+), 36 deletions(-)
>