Re: [PATCH net-next 2/3] dt-bindings: net: micrel: Configure latency values and timestamping check for LAN8814 phy

Richard Cochran
2022-03-12T02:48:39Z

On Fri, Mar 11, 2022 at 03:21:58PM +0000, Woojung.Huh@microchip.com wrote:

> If you are referring to the delayAsymmetry of ptp4l,

No, really, I'm not.

PTP4l(8) System Manager's Manual PTP4l(8)

NAME
ptp4l - PTP Boundary/Ordinary/Transparent Clock

...

egressLatency
Specifies the difference in nanoseconds between the actual
transmission time at the reference plane and the reported trans‐
mit time stamp. This value will be added to egress time stamps
obtained from the hardware. The default is 0.

ingressLatency
Specifies the difference in nanoseconds between the reported re‐
ceive time stamp and the actual reception time at reference
plane. This value will be subtracted from ingress time stamps
obtained from the hardware. The default is 0.

> So, this latency should (hopefully) be not-much-change in the same board after manufactured.

Please read the papers on this topic. I posted links in another reply
in this thread.

> Of cause, all values may be small enough to ignore though.
> Do I miss something here?

Yes, you miss the point entirely. PHY delays are relatively large and
cannot be even measured in some cases. However, for well behaved
PHYs, the user space stack already covers the configuration.

Thanks,
Richard