Re: [PATCH v3 22/39] x86/ibt: Add IBT feature, MSR and #CP handling

Peter Zijlstra
2022-03-04T20:39:38Z

On Fri, Mar 04, 2022 at 10:07:20AM -0800, Josh Poimboeuf wrote:
> On Thu, Mar 03, 2022 at 12:23:43PM +0100, Peter Zijlstra wrote:
> > @@ -310,6 +311,7 @@ void machine_kexec(struct kimage *image)
> > /* Interrupts aren't acceptable while we reboot */
> > local_irq_disable();
> > hw_breakpoint_disable();
> > + cet_disable();
> >
> > if (image->preserve_context) {
> > #ifdef CONFIG_X86_IO_APIC
> > --- a/arch/x86/kernel/relocate_kernel_64.S
> > +++ b/arch/x86/kernel/relocate_kernel_64.S
> > @@ -115,6 +115,14 @@ SYM_CODE_START_LOCAL_NOALIGN(identity_ma
> > pushq %rdx
> >
> > /*
> > + * Clear X86_CR4_CET (if it was set) such that we can clear CR0_WP
> > + * below.
> > + */
> > + movq %cr4, %rax
> > + andq $~(X86_CR4_CET), %rax
> > + movq %rax, %cr4
> > +
> > + /*
> > * Set cr0 to a known state:
> > * - Paging enabled
> > * - Alignment check disabled
>
> This probably belongs in a separate patch...

A x86/ibt,kexec patch has just been born...