[PATCH v3 10/18] ARM: dts: qcom: add saw for l2 cache and kraitcc for ipq8064

Ansuel Smith
2022-03-09T19:16:25Z

Add saw compatible for l2 cache and kraitcc node for ipq8064 dtsi.
Also declare clock-output-names for acc0 and acc1 and qsb fixed clock
for the secondary mux.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Tested-by: Jonathan McDowell <noodles@earth.li>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 34 +++++++++++++++++++++++++++--
1 file changed, 32 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index c579fb09e768..7df1c1482220 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -298,6 +298,12 @@ smem: smem@41000000 {
};

clocks {
+ qsb: qsb {
+ compatible = "fixed-clock";
+ clock-frequency = <384000000>;
+ #clock-cells = <0>;
+ };
+
cxo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -504,11 +510,19 @@ IRQ_TYPE_EDGE_RISING)>,
acc0: clock-controller@2088000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
+ clock-output-names = "acpu0_aux";
+ clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
+ clock-names = "pll8_vote", "pxo";
+ #clock-cells = <0>;
};

acc1: clock-controller@2098000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
+ clock-output-names = "acpu1_aux";
+ clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
+ clock-names = "pll8_vote", "pxo";
+ #clock-cells = <0>;
};

adm_dma: dma-controller@18300000 {
@@ -532,17 +546,23 @@ adm_dma: dma-controller@18300000 {
};

saw0: regulator@2089000 {
- compatible = "qcom,saw2";
+ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
regulator;
};

saw1: regulator@2099000 {
- compatible = "qcom,saw2";
+ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
regulator;
};

+ saw_l2: regulator@02012000 {
+ compatible = "qcom,saw2", "syscon";
+ reg = <0x02012000 0x1000>;
+ regulator;
+ };
+
gsbi2: gsbi@12480000 {
compatible = "qcom,gsbi-v1.0.0";
cell-index = <2>;
@@ -899,6 +919,16 @@ l2cc: clock-controller@2011000 {
clock-output-names = "acpu_l2_aux";
};

+ kraitcc: clock-controller {
+ compatible = "qcom,krait-cc-v1";
+ clocks = <&gcc PLL9>, <&gcc PLL10>, <&gcc PLL12>,
+ <&acc0>, <&acc1>, <&l2cc>, <&qsb>;
+ clock-names = "hfpll0", "hfpll1", "hfpll_l2",
+ "acpu0_aux", "acpu1_aux", "acpu_l2_aux",
+ "qsb";
+ #clock-cells = <1>;
+ };
+
lcc: clock-controller@28000000 {
compatible = "qcom,lcc-ipq8064";
reg = <0x28000000 0x1000>;
--
2.34.1