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Wed, 16 Mar 2022 14:54:32 +0000 Date: Wed, 16 Mar 2022 14:54:03 +0000 From: Andre Przywara To: Marc Zyngier Cc: linux-kernel@vger.kernel.org, Lorenzo Pieralisi , Thomas Gleixner , Eric Auger Subject: Re: [PATCH 3/3] irqchip/gic-v3: Relax polling of GIC{R,D}_CTLR.RWP Message-ID: <20220316145403.51475e25@slackpad.lan> In-Reply-To: <20220315165034.794482-4-maz@kernel.org> References: <20220315165034.794482-1-maz@kernel.org> <20220315165034.794482-4-maz@kernel.org> Organization: Arm Ltd. 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Don't we need an explicit call to wait_for_rwp() now for: gic_irq_set_irqchip_state(IRQCHIP_STATE_MASKED, true) ? The rest looks fine to me. Thanks, Andre > > Signed-off-by: Marc Zyngier > --- > drivers/irqchip/irq-gic-v3.c | 28 +++++++++++----------------- > 1 file changed, 11 insertions(+), 17 deletions(-) > > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c > index 363bfe172033..05ff7fef64cb 100644 > --- a/drivers/irqchip/irq-gic-v3.c > +++ b/drivers/irqchip/irq-gic-v3.c > @@ -352,28 +352,27 @@ static int gic_peek_irq(struct irq_data *d, u32 off= set) > > static void gic_poke_irq(struct irq_data *d, u32 offset) > { > - void (*rwp_wait)(void); > void __iomem *base; > u32 index, mask; > > offset =3D convert_offset_index(d, offset, &index); > mask =3D 1 << (index % 32); > > - if (gic_irq_in_rdist(d)) { > + if (gic_irq_in_rdist(d)) > base =3D gic_data_rdist_sgi_base(); > - rwp_wait =3D gic_redist_wait_for_rwp; > - } else { > + else > base =3D gic_data.dist_base; > - rwp_wait =3D gic_dist_wait_for_rwp; > - } > > writel_relaxed(mask, base + offset + (index / 32) * 4); > - rwp_wait(); > } > > static void gic_mask_irq(struct irq_data *d) > { > gic_poke_irq(d, GICD_ICENABLER); > + if (gic_irq_in_rdist(d)) > + gic_redist_wait_for_rwp(); > + else > + gic_dist_wait_for_rwp(); > } > > static void gic_eoimode1_mask_irq(struct irq_data *d) > @@ -574,7 +573,6 @@ static int gic_set_type(struct irq_data *d, unsigned = int type) > { > enum gic_intid_range range; > unsigned int irq =3D gic_irq(d); > - void (*rwp_wait)(void); > void __iomem *base; > u32 offset, index; > int ret; > @@ -590,17 +588,14 @@ static int gic_set_type(struct irq_data *d, unsigne= d int type) > type !=3D IRQ_TYPE_LEVEL_HIGH && type !=3D IRQ_TYPE_EDGE_RISING= ) > return -EINVAL; > > - if (gic_irq_in_rdist(d)) { > + if (gic_irq_in_rdist(d)) > base =3D gic_data_rdist_sgi_base(); > - rwp_wait =3D gic_redist_wait_for_rwp; > - } else { > + else > base =3D gic_data.dist_base; > - rwp_wait =3D gic_dist_wait_for_rwp; > - } > > offset =3D convert_offset_index(d, GICD_ICFGR, &index); > > - ret =3D gic_configure_irq(index, type, base + offset, rwp_wait); > + ret =3D gic_configure_irq(index, type, base + offset, NULL); > if (ret && (range =3D=3D PPI_RANGE || range =3D=3D EPPI_RANGE)) { > /* Misconfigured PPIs are usually not fatal */ > pr_warn("GIC: PPI INTID%d is secure or misconfigured\n", ir= q); > @@ -808,7 +803,7 @@ static void __init gic_dist_init(void) > writel_relaxed(GICD_INT_DEF_PRI_X4, base + GICD_IPRIORITYRn= E + i); > > /* Now do the common stuff, and wait for the distributor to drain *= / > - gic_dist_config(base, GIC_LINE_NR, gic_dist_wait_for_rwp); > + gic_dist_config(base, GIC_LINE_NR, NULL); > > val =3D GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_= G1; > if (gic_data.rdists.gicd_typer2 & GICD_TYPER2_nASSGIcap) { > @@ -818,6 +813,7 @@ static void __init gic_dist_init(void) > > /* Enable distributor with ARE, Group1 */ > writel_relaxed(val, base + GICD_CTLR); > + gic_dist_wait_for_rwp(); > > /* > * Set all global interrupts to the boot CPU only. ARE must be > @@ -1293,8 +1289,6 @@ static int gic_set_affinity(struct irq_data *d, con= st struct cpumask *mask_val, > */ > if (enabled) > gic_unmask_irq(d); > - else > - gic_dist_wait_for_rwp(); > > irq_data_update_effective_affinity(d, cpumask_of(cpu)); > IMPORTANT NOTICE: The contents of this email and any attachments are confid= ential and may also be privileged. If you are not the intended recipient, p= lease notify the sender immediately and do not disclose the contents to any= other person, use it for any purpose, or store or copy the information in = any medium. Thank you.