* [PATCH] RISC-V: Enable perf events by default
@ 2022-03-23 9:00 Anup Patel
2022-03-23 16:34 ` Atish Patra
0 siblings, 1 reply; 3+ messages in thread
From: Anup Patel @ 2022-03-23 9:00 UTC (permalink / raw)
To: Palmer Dabbelt, Paul Walmsley
Cc: Atish Patra, Alistair Francis, Anup Patel, linux-riscv,
linux-kernel, Anup Patel
Let us enable perf events by default in RV32 and RV64 defconfigs
so that we can use RISC-V PMU drivers on various RISC-V platforms.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
arch/riscv/configs/defconfig | 1 +
arch/riscv/configs/rv32_defconfig | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index f120fcc43d0a..57aaedc7cf74 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -15,6 +15,7 @@ CONFIG_CHECKPOINT_RESTORE=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
# CONFIG_SYSFS_SYSCALL is not set
+CONFIG_PERF_EVENTS=y
CONFIG_SOC_MICROCHIP_POLARFIRE=y
CONFIG_SOC_SIFIVE=y
CONFIG_SOC_VIRT=y
diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_defconfig
index 8b56a7f1eb06..21d422e740d5 100644
--- a/arch/riscv/configs/rv32_defconfig
+++ b/arch/riscv/configs/rv32_defconfig
@@ -15,6 +15,7 @@ CONFIG_CHECKPOINT_RESTORE=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
# CONFIG_SYSFS_SYSCALL is not set
+CONFIG_PERF_EVENTS=y
CONFIG_SOC_SIFIVE=y
CONFIG_SOC_VIRT=y
CONFIG_ARCH_RV32I=y
--
2.25.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] RISC-V: Enable perf events by default
2022-03-23 9:00 [PATCH] RISC-V: Enable perf events by default Anup Patel
@ 2022-03-23 16:34 ` Atish Patra
2022-03-24 5:26 ` Anup Patel
0 siblings, 1 reply; 3+ messages in thread
From: Atish Patra @ 2022-03-23 16:34 UTC (permalink / raw)
To: Anup Patel
Cc: Palmer Dabbelt, Paul Walmsley, Alistair Francis, Anup Patel,
linux-riscv, linux-kernel@vger.kernel.org List
On Wed, Mar 23, 2022 at 2:00 AM Anup Patel <apatel@ventanamicro.com> wrote:
>
> Let us enable perf events by default in RV32 and RV64 defconfigs
> so that we can use RISC-V PMU drivers on various RISC-V platforms.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
> arch/riscv/configs/defconfig | 1 +
> arch/riscv/configs/rv32_defconfig | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index f120fcc43d0a..57aaedc7cf74 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -15,6 +15,7 @@ CONFIG_CHECKPOINT_RESTORE=y
> CONFIG_BLK_DEV_INITRD=y
> CONFIG_EXPERT=y
> # CONFIG_SYSFS_SYSCALL is not set
> +CONFIG_PERF_EVENTS=y
> CONFIG_SOC_MICROCHIP_POLARFIRE=y
> CONFIG_SOC_SIFIVE=y
> CONFIG_SOC_VIRT=y
> diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_defconfig
> index 8b56a7f1eb06..21d422e740d5 100644
> --- a/arch/riscv/configs/rv32_defconfig
> +++ b/arch/riscv/configs/rv32_defconfig
> @@ -15,6 +15,7 @@ CONFIG_CHECKPOINT_RESTORE=y
> CONFIG_BLK_DEV_INITRD=y
> CONFIG_EXPERT=y
> # CONFIG_SYSFS_SYSCALL is not set
> +CONFIG_PERF_EVENTS=y
> CONFIG_SOC_SIFIVE=y
> CONFIG_SOC_VIRT=y
> CONFIG_ARCH_RV32I=y
> --
> 2.25.1
>
I think it is better to enable perf events by adding CONFIG_PROFILING
to the defconfig similar to other ISAs.
--
Regards,
Atish
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] RISC-V: Enable perf events by default
2022-03-23 16:34 ` Atish Patra
@ 2022-03-24 5:26 ` Anup Patel
0 siblings, 0 replies; 3+ messages in thread
From: Anup Patel @ 2022-03-24 5:26 UTC (permalink / raw)
To: Atish Patra
Cc: Anup Patel, Palmer Dabbelt, Paul Walmsley, Alistair Francis,
linux-riscv, linux-kernel@vger.kernel.org List
On Wed, Mar 23, 2022 at 10:04 PM Atish Patra <atishp@atishpatra.org> wrote:
>
> On Wed, Mar 23, 2022 at 2:00 AM Anup Patel <apatel@ventanamicro.com> wrote:
> >
> > Let us enable perf events by default in RV32 and RV64 defconfigs
> > so that we can use RISC-V PMU drivers on various RISC-V platforms.
> >
> > Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> > ---
> > arch/riscv/configs/defconfig | 1 +
> > arch/riscv/configs/rv32_defconfig | 1 +
> > 2 files changed, 2 insertions(+)
> >
> > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> > index f120fcc43d0a..57aaedc7cf74 100644
> > --- a/arch/riscv/configs/defconfig
> > +++ b/arch/riscv/configs/defconfig
> > @@ -15,6 +15,7 @@ CONFIG_CHECKPOINT_RESTORE=y
> > CONFIG_BLK_DEV_INITRD=y
> > CONFIG_EXPERT=y
> > # CONFIG_SYSFS_SYSCALL is not set
> > +CONFIG_PERF_EVENTS=y
> > CONFIG_SOC_MICROCHIP_POLARFIRE=y
> > CONFIG_SOC_SIFIVE=y
> > CONFIG_SOC_VIRT=y
> > diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_defconfig
> > index 8b56a7f1eb06..21d422e740d5 100644
> > --- a/arch/riscv/configs/rv32_defconfig
> > +++ b/arch/riscv/configs/rv32_defconfig
> > @@ -15,6 +15,7 @@ CONFIG_CHECKPOINT_RESTORE=y
> > CONFIG_BLK_DEV_INITRD=y
> > CONFIG_EXPERT=y
> > # CONFIG_SYSFS_SYSCALL is not set
> > +CONFIG_PERF_EVENTS=y
> > CONFIG_SOC_SIFIVE=y
> > CONFIG_SOC_VIRT=y
> > CONFIG_ARCH_RV32I=y
> > --
> > 2.25.1
> >
>
> I think it is better to enable perf events by adding CONFIG_PROFILING
> to the defconfig similar to other ISAs.
Sure, I will update this patch like you suggested.
Regards,
Anup
>
> --
> Regards,
> Atish
^ permalink raw reply [flat|nested] 3+ messages in thread
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