From: Heiko Stuebner <heiko@sntech.de>
To: palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
wefu@redhat.com, liush@allwinnertech.com, guoren@kernel.org,
atishp@atishpatra.org, anup@brainfault.org, drew@beagleboard.org,
hch@lst.de, arnd@arndb.de, wens@csie.org, maxime@cerno.tech,
gfavor@ventanamicro.com, andrea.mondelli@huawei.com,
behrensj@mit.edu, xinhaoqu@huawei.com, mick@ics.forth.gr,
allen.baum@esperantotech.com, jscheid@ventanamicro.com,
rtrauben@gmail.com, samuel@sholland.org, cmuellner@linux.com,
philipp.tomsich@vrull.eu, Heiko Stuebner <heiko@sntech.de>
Subject: [PATCH v8 06/14] riscv: extend concatenated alternatives-lines to the same length
Date: Thu, 24 Mar 2022 01:07:02 +0100 [thread overview]
Message-ID: <20220324000710.575331-7-heiko@sntech.de> (raw)
In-Reply-To: <20220324000710.575331-1-heiko@sntech.de>
ALT_NEW_CONTENT already uses same-length assembler lines, so
extend this to the other elements as well.
This makes it more readable when these elements need to be extended
in the future.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/riscv/include/asm/alternative-macros.h | 30 ++++++++++-----------
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h
index 259d8246d612..25b4559d743b 100644
--- a/arch/riscv/include/asm/alternative-macros.h
+++ b/arch/riscv/include/asm/alternative-macros.h
@@ -58,14 +58,14 @@
#include <asm/asm.h>
#include <linux/stringify.h>
-#define ALT_ENTRY(oldptr, newptr, vendor_id, errata_id, newlen) \
- RISCV_PTR " " oldptr "\n" \
- RISCV_PTR " " newptr "\n" \
- REG_ASM " " vendor_id "\n" \
- REG_ASM " " newlen "\n" \
+#define ALT_ENTRY(oldptr, newptr, vendor_id, errata_id, newlen) \
+ RISCV_PTR " " oldptr "\n" \
+ RISCV_PTR " " newptr "\n" \
+ REG_ASM " " vendor_id "\n" \
+ REG_ASM " " newlen "\n" \
".word " errata_id "\n"
-#define ALT_NEW_CONTENT(vendor_id, errata_id, enable, new_c) \
+#define ALT_NEW_CONTENT(vendor_id, errata_id, enable, new_c) \
".if " __stringify(enable) " == 1\n" \
".pushsection .alternative, \"a\"\n" \
ALT_ENTRY("886b", "888f", __stringify(vendor_id), __stringify(errata_id), "889f - 888f") \
@@ -79,21 +79,21 @@
".org . - (889b - 888b) + (887b - 886b)\n" \
".endif\n"
-#define __ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, enable) \
- "886 :\n" \
- old_c "\n" \
- "887 :\n" \
+#define __ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, enable) \
+ "886 :\n" \
+ old_c "\n" \
+ "887 :\n" \
ALT_NEW_CONTENT(vendor_id, errata_id, enable, new_c)
-#define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k) \
+#define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k) \
__ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, IS_ENABLED(CONFIG_k))
#define __ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, errata_id_1, enable_1, \
new_c_2, vendor_id_2, errata_id_2, enable_2) \
- "886 :\n" \
- old_c "\n" \
- "887 :\n" \
- ALT_NEW_CONTENT(vendor_id_1, errata_id_1, enable_1, new_c_1) \
+ "886 :\n" \
+ old_c "\n" \
+ "887 :\n" \
+ ALT_NEW_CONTENT(vendor_id_1, errata_id_1, enable_1, new_c_1) \
ALT_NEW_CONTENT(vendor_id_2, errata_id_2, enable_2, new_c_2)
#define _ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, errata_id_1, CONFIG_k_1, \
--
2.35.1
next prev parent reply other threads:[~2022-03-24 0:07 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-24 0:06 [PATCH v8 00/14] riscv: support for Svpbmt and D1 memory types Heiko Stuebner
2022-03-24 0:06 ` [PATCH v8 01/14] riscv: prevent null-pointer dereference with sbi_remote_fence_i Heiko Stuebner
2022-03-31 9:51 ` Christoph Hellwig
2022-03-31 12:28 ` Heiko Stübner
2022-03-31 12:33 ` Christoph Hellwig
2022-04-07 18:50 ` Heiko Stübner
2022-03-24 0:06 ` [PATCH v8 02/14] riscv: integrate alternatives better into the main architecture Heiko Stuebner
2022-03-31 9:53 ` Christoph Hellwig
2022-03-24 0:06 ` [PATCH v8 03/14] riscv: allow different stages with alternatives Heiko Stuebner
2022-03-24 0:07 ` [PATCH v8 04/14] riscv: implement module alternatives Heiko Stuebner
2022-03-24 0:07 ` [PATCH v8 05/14] riscv: implement ALTERNATIVE_2 macro Heiko Stuebner
2022-03-31 9:56 ` Christoph Hellwig
2022-03-24 0:07 ` Heiko Stuebner [this message]
2022-03-24 0:07 ` [PATCH v8 07/14] riscv: prevent compressed instructions in alternatives Heiko Stuebner
2022-03-31 9:56 ` Christoph Hellwig
2022-03-24 0:07 ` [PATCH v8 08/14] riscv: move boot alternatives to after fill_hwcap Heiko Stuebner
2022-03-31 9:57 ` Christoph Hellwig
2022-03-24 0:07 ` [PATCH v8 09/14] riscv: Fix accessing pfn bits in PTEs for non-32bit variants Heiko Stuebner
2022-03-31 9:59 ` Christoph Hellwig
2022-03-24 0:07 ` [PATCH v8 10/14] riscv: add cpufeature handling via alternatives Heiko Stuebner
2022-03-31 10:01 ` Christoph Hellwig
2022-04-08 16:13 ` Heiko Stübner
2022-03-24 0:07 ` [PATCH v8 11/14] riscv: add RISC-V Svpbmt extension support Heiko Stuebner
2022-03-31 10:03 ` Christoph Hellwig
2022-03-31 12:19 ` Heiko Stübner
2022-03-31 12:27 ` Christoph Hellwig
2022-03-31 12:29 ` Christoph Hellwig
2022-03-24 0:07 ` [PATCH v8 12/14] riscv: remove FIXMAP_PAGE_IO and fall back to its default value Heiko Stuebner
2022-03-31 10:03 ` Christoph Hellwig
2022-03-24 0:07 ` [PATCH v8 13/14] riscv: don't use global static vars to store alternative data Heiko Stuebner
2022-03-24 0:07 ` [PATCH v8 14/14] riscv: add memory-type errata for T-Head Heiko Stuebner
2022-03-31 2:24 ` [PATCH v8 00/14] riscv: support for Svpbmt and D1 memory types Palmer Dabbelt
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