Re: [PATCH v4] perf/x86/amd: Don't touch the Host-only bit inside the guest hypervisor

Dongli Si
2022-03-27T10:57:16Z

On 24/03/2022 10:42, Peter Zijlstra wrote:
> So I had to go and read the original commit to figure out wth this code
> is supposed to be doing. I'm thinking this all can use a wee comment.

Hi Peter, I will add a wee comment to clarifies things.

> Also, the above is very ambiguous as to what it does. Specifically if we
> don't set perf_ctr_virt_mask, then what is the actual value (yes, I
> know, but its not very clear is it). Also, if we don't in fact change
> perf_ctr_virt_mask then these following two lines:
>
> >
> > /* Reload all events */
> > amd_pmu_disable_all();
> amd_pmu_enable_all(0);
>
> are somewhat completely pointless, no?

Thank you for pointing out the problem with my patch.

> So can we please get a patch that clarifies things instead of making
> things even more obscure?

The following is an improved patch, is it good?

Regards,
Dongli

---
From: Dongli Si <sidongli1997@gmail.com>

With nested virtualization on AMD Milan, if "perf record" is run in an
L1 hypervisor with an L2 guest, the following warning is emitted in
the L1 guest.

[] unchecked MSR access error: WRMSR to 0xc0010200 (tried to write 0x0000020000510076)
at rIP: 0xffffffff81003a50 (x86_pmu_enable_all+0x60/0x100)
[] Call Trace:
[] <IRQ>
[] ? x86_pmu_enable+0x146/0x300
[] __perf_install_in_context+0x150/0x170

The AMD64_EVENTSEL_HOSTONLY bit is defined and used on the host (L0),
while the L1 hypervisor Performance Monitor Unit should avoid such use.

Fixes: 1018faa6cf23 ("perf/x86/kvm: Fix Host-Only/Guest-Only counting with SVM disabled")
Signed-off-by: Dongli Si <sidongli1997@gmail.com>
Tested-by: Liam Merwick <liam.merwick@oracle.com>
Reviewed-by: Liam Merwick <liam.merwick@oracle.com>
---
v5: Add a wee comment to clarifies things and improve code
v4: https://lore.kernel.org/all/20220320002106.1800166-1-sidongli1997@gmail.com/
v3: https://lore.kernel.org/all/20220314042254.1487836-1-sidongli1997@gmail.com/
v2: https://lore.kernel.org/all/20220310183404.1291725-1-sidongli1997@gmail.com/
v1: https://lore.kernel.org/all/20220227132640.3-1-sidongli1997@gmail.com/

arch/x86/events/amd/core.c | 13 +++++++++++++
1 file changed, 13 insertions(+)

diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
index 9687a8aef01c..5a1657c684f0 100644
--- a/arch/x86/events/amd/core.c
+++ b/arch/x86/events/amd/core.c
@@ -8,6 +8,7 @@
#include <linux/jiffies.h>
#include <asm/apicdef.h>
#include <asm/nmi.h>
+#include <asm/hypervisor.h>

#include "../perf_event.h"

@@ -1023,10 +1024,16 @@ __init int amd_pmu_init(void)
return 0;
}

+/*
+ * Set the Host-only bit when virtualization is enabled on the Host Hypervisor
+ */
void amd_pmu_enable_virt(void)
{
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);

+ if (!hypervisor_is_type(X86_HYPER_NATIVE))
+ return;
+
cpuc->perf_ctr_virt_mask = 0;

/* Reload all events */
@@ -1035,10 +1042,16 @@ void amd_pmu_enable_virt(void)
}
EXPORT_SYMBOL_GPL(amd_pmu_enable_virt);

+/*
+ * Mask the Host-only bit when virtualization is disabled on the Host Hypervisor
+ */
void amd_pmu_disable_virt(void)
{
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);

+ if (!hypervisor_is_type(X86_HYPER_NATIVE))
+ return;
+
/*
* We only mask out the Host-only bit so that host-only counting works
* when SVM is disabled. If someone sets up a guest-only counter when
--
2.32.0