From: Christoph Hellwig <hch@lst.de>
To: Heiko Stuebner <heiko@sntech.de>
Cc: palmer@dabbelt.com, paul.walmsley@sifive.com,
aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, wefu@redhat.com,
liush@allwinnertech.com, guoren@kernel.org,
atishp@atishpatra.org, anup@brainfault.org, drew@beagleboard.org,
hch@lst.de, arnd@arndb.de, wens@csie.org, maxime@cerno.tech,
gfavor@ventanamicro.com, andrea.mondelli@huawei.com,
behrensj@mit.edu, xinhaoqu@huawei.com, mick@ics.forth.gr,
allen.baum@esperantotech.com, jscheid@ventanamicro.com,
rtrauben@gmail.com, samuel@sholland.org, cmuellner@linux.com,
philipp.tomsich@vrull.eu
Subject: Re: [PATCH v8 09/14] riscv: Fix accessing pfn bits in PTEs for non-32bit variants
Date: Thu, 31 Mar 2022 11:59:37 +0200 [thread overview]
Message-ID: <20220331095937.GF23422@lst.de> (raw)
In-Reply-To: <20220324000710.575331-10-heiko@sntech.de>
On Thu, Mar 24, 2022 at 01:07:05AM +0100, Heiko Stuebner wrote:
> On rv32 the PFN part of PTEs is defined to use bits [xlen-1:10]
> while on rv64 it is defined to use bits [53:10], leaving [63:54]
> as reserved.
>
> With upcoming optional extensions like svpbmt these previously
> reserved bits will get used so simply right-shifting the PTE
> to get the PFN won't be enough.
>
> So introduce a _PAGE_PFN_MASK constant to mask the correct bits
> for both rv32 and rv64 before shifting.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
> arch/riscv/include/asm/pgtable-32.h | 8 ++++++++
> arch/riscv/include/asm/pgtable-64.h | 14 +++++++++++---
> arch/riscv/include/asm/pgtable-bits.h | 6 ------
> arch/riscv/include/asm/pgtable.h | 6 +++---
> 4 files changed, 22 insertions(+), 12 deletions(-)
>
> diff --git a/arch/riscv/include/asm/pgtable-32.h b/arch/riscv/include/asm/pgtable-32.h
> index 5b2e79e5bfa5..e266a4fe7f43 100644
> --- a/arch/riscv/include/asm/pgtable-32.h
> +++ b/arch/riscv/include/asm/pgtable-32.h
> @@ -7,6 +7,7 @@
> #define _ASM_RISCV_PGTABLE_32_H
>
> #include <asm-generic/pgtable-nopmd.h>
> +#include <linux/bits.h>
> #include <linux/const.h>
>
> /* Size of region mapped by a page global directory */
> @@ -16,4 +17,11 @@
>
> #define MAX_POSSIBLE_PHYSMEM_BITS 34
>
> +/*
> + * rv32 PTE format:
> + * | XLEN-1 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
> + * PFN reserved for SW D A G U X W R V
> + */
> +#define _PAGE_PFN_MASK GENMASK(31, 10)
I have to say I really hate this obsfucating GENMASK macro, but it
does have a few other uses in the riscv code.
> +/*
> + * rv64 PTE format:
> + * | 63 | 62 61 | 60 54 | 53 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
> + * N MT RSV PFN reserved for SW D A G U X W R V
> + */
>
> +#define _PAGE_PFN_MASK GENMASK(53, 10)
> +
> static inline int pud_present(pud_t pud)
> {
> return (pud_val(pud) & _PAGE_PRESENT);
> @@ -91,12 +99,12 @@ static inline unsigned long _pud_pfn(pud_t pud)
>
> static inline pmd_t *pud_pgtable(pud_t pud)
> {
> - return (pmd_t *)pfn_to_virt(pud_val(pud) >> _PAGE_PFN_SHIFT);
> + return (pmd_t *)pfn_to_virt((pud_val(pud) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT);
Lots of overly long lins making this pretty unreadable.
But in general the (pfn & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT logic
really should have a helper anyway.
next prev parent reply other threads:[~2022-03-31 9:59 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-24 0:06 [PATCH v8 00/14] riscv: support for Svpbmt and D1 memory types Heiko Stuebner
2022-03-24 0:06 ` [PATCH v8 01/14] riscv: prevent null-pointer dereference with sbi_remote_fence_i Heiko Stuebner
2022-03-31 9:51 ` Christoph Hellwig
2022-03-31 12:28 ` Heiko Stübner
2022-03-31 12:33 ` Christoph Hellwig
2022-04-07 18:50 ` Heiko Stübner
2022-03-24 0:06 ` [PATCH v8 02/14] riscv: integrate alternatives better into the main architecture Heiko Stuebner
2022-03-31 9:53 ` Christoph Hellwig
2022-03-24 0:06 ` [PATCH v8 03/14] riscv: allow different stages with alternatives Heiko Stuebner
2022-03-24 0:07 ` [PATCH v8 04/14] riscv: implement module alternatives Heiko Stuebner
2022-03-24 0:07 ` [PATCH v8 05/14] riscv: implement ALTERNATIVE_2 macro Heiko Stuebner
2022-03-31 9:56 ` Christoph Hellwig
2022-03-24 0:07 ` [PATCH v8 06/14] riscv: extend concatenated alternatives-lines to the same length Heiko Stuebner
2022-03-24 0:07 ` [PATCH v8 07/14] riscv: prevent compressed instructions in alternatives Heiko Stuebner
2022-03-31 9:56 ` Christoph Hellwig
2022-03-24 0:07 ` [PATCH v8 08/14] riscv: move boot alternatives to after fill_hwcap Heiko Stuebner
2022-03-31 9:57 ` Christoph Hellwig
2022-03-24 0:07 ` [PATCH v8 09/14] riscv: Fix accessing pfn bits in PTEs for non-32bit variants Heiko Stuebner
2022-03-31 9:59 ` Christoph Hellwig [this message]
2022-03-24 0:07 ` [PATCH v8 10/14] riscv: add cpufeature handling via alternatives Heiko Stuebner
2022-03-31 10:01 ` Christoph Hellwig
2022-04-08 16:13 ` Heiko Stübner
2022-03-24 0:07 ` [PATCH v8 11/14] riscv: add RISC-V Svpbmt extension support Heiko Stuebner
2022-03-31 10:03 ` Christoph Hellwig
2022-03-31 12:19 ` Heiko Stübner
2022-03-31 12:27 ` Christoph Hellwig
2022-03-31 12:29 ` Christoph Hellwig
2022-03-24 0:07 ` [PATCH v8 12/14] riscv: remove FIXMAP_PAGE_IO and fall back to its default value Heiko Stuebner
2022-03-31 10:03 ` Christoph Hellwig
2022-03-24 0:07 ` [PATCH v8 13/14] riscv: don't use global static vars to store alternative data Heiko Stuebner
2022-03-24 0:07 ` [PATCH v8 14/14] riscv: add memory-type errata for T-Head Heiko Stuebner
2022-03-31 2:24 ` [PATCH v8 00/14] riscv: support for Svpbmt and D1 memory types Palmer Dabbelt
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