[PATCH 5.16 0701/1017] pinctrl: microchip-sgpio: lock RMW access

Greg Kroah-Hartman
2022-04-05T13:24:06Z

From: Michael Walle <michael@walle.cc>

[ Upstream commit 7996c5f5ec7a20b3f6b8fae93fcf3cb8f1c01743 ]

Protect any RMW access to the registers by a spinlock.

Fixes: 7e5ea974e61c ("pinctrl: pinctrl-microchip-sgpio: Add pinctrl driver for Microsemi Serial GPIO")
Signed-off-by: Michael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20220226204507.2511633-2-michael@walle.cc
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/pinctrl/pinctrl-microchip-sgpio.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-microchip-sgpio.c b/drivers/pinctrl/pinctrl-microchip-sgpio.c
index 78765faa245a..dfa374195694 100644
--- a/drivers/pinctrl/pinctrl-microchip-sgpio.c
+++ b/drivers/pinctrl/pinctrl-microchip-sgpio.c
@@ -18,6 +18,7 @@
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/reset.h>
+#include <linux/spinlock.h>

#include "core.h"
#include "pinconf.h"
@@ -115,6 +116,7 @@ struct sgpio_priv {
u32 clock;
u32 __iomem *regs;
const struct sgpio_properties *properties;
+ spinlock_t lock;
};

struct sgpio_port_addr {
@@ -216,6 +218,7 @@ static void sgpio_output_set(struct sgpio_priv *priv,
int value)
{
unsigned int bit = SGPIO_SRC_BITS * addr->bit;
+ unsigned long flags;
u32 clr, set;

switch (priv->properties->arch) {
@@ -234,7 +237,10 @@ static void sgpio_output_set(struct sgpio_priv *priv,
default:
return;
}
+
+ spin_lock_irqsave(&priv->lock, flags);
sgpio_clrsetbits(priv, REG_PORT_CONFIG, addr->port, clr, set);
+ spin_unlock_irqrestore(&priv->lock, flags);
}

static int sgpio_output_get(struct sgpio_priv *priv,
@@ -562,10 +568,13 @@ static void microchip_sgpio_irq_settype(struct irq_data *data,
struct sgpio_bank *bank = gpiochip_get_data(chip);
unsigned int gpio = irqd_to_hwirq(data);
struct sgpio_port_addr addr;
+ unsigned long flags;
u32 ena;

sgpio_pin_to_addr(bank->priv, gpio, &addr);

+ spin_lock_irqsave(&bank->priv->lock, flags);
+
/* Disable interrupt while changing type */
ena = sgpio_readl(bank->priv, REG_INT_ENABLE, addr.bit);
sgpio_writel(bank->priv, ena & ~BIT(addr.port), REG_INT_ENABLE, addr.bit);
@@ -582,6 +591,8 @@ static void microchip_sgpio_irq_settype(struct irq_data *data,

/* Possibly re-enable interrupts */
sgpio_writel(bank->priv, ena, REG_INT_ENABLE, addr.bit);
+
+ spin_unlock_irqrestore(&bank->priv->lock, flags);
}

static void microchip_sgpio_irq_setreg(struct irq_data *data,
@@ -592,13 +603,16 @@ static void microchip_sgpio_irq_setreg(struct irq_data *data,
struct sgpio_bank *bank = gpiochip_get_data(chip);
unsigned int gpio = irqd_to_hwirq(data);
struct sgpio_port_addr addr;
+ unsigned long flags;

sgpio_pin_to_addr(bank->priv, gpio, &addr);

+ spin_lock_irqsave(&bank->priv->lock, flags);
if (clear)
sgpio_clrsetbits(bank->priv, reg, addr.bit, BIT(addr.port), 0);
else
sgpio_clrsetbits(bank->priv, reg, addr.bit, 0, BIT(addr.port));
+ spin_unlock_irqrestore(&bank->priv->lock, flags);
}

static void microchip_sgpio_irq_mask(struct irq_data *data)
@@ -814,6 +828,7 @@ static int microchip_sgpio_probe(struct platform_device *pdev)
return -ENOMEM;

priv->dev = dev;
+ spin_lock_init(&priv->lock);

reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch");
if (IS_ERR(reset))
--
2.34.1