From: Marc Zyngier <maz@kernel.org>
To: linux-kernel@vger.kernel.org
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Andre Przywara <andre.przywara@arm.com>,
Thomas Gleixner <tglx@linutronix.de>,
Eric Auger <eric.auger@redhat.com>
Subject: [PATCH v2 1/3] irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR,CES}
Date: Tue, 5 Apr 2022 19:38:55 +0100 [thread overview]
Message-ID: <20220405183857.205960-2-maz@kernel.org> (raw)
In-Reply-To: <20220405183857.205960-1-maz@kernel.org>
As we're about to expose GICR_CTLR.{IR,CES} to guests, populate
the include file with the architectural values.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
include/linux/irqchip/arm-gic-v3.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index 12d91f0dedf9..728691365464 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -127,6 +127,8 @@
#define GICR_PIDR2 GICD_PIDR2
#define GICR_CTLR_ENABLE_LPIS (1UL << 0)
+#define GICR_CTLR_CES (1UL << 1)
+#define GICR_CTLR_IR (1UL << 2)
#define GICR_CTLR_RWP (1UL << 3)
#define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff)
--
2.34.1
next prev parent reply other threads:[~2022-04-06 0:17 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-05 18:38 [PATCH v2 0/3] irqchip/gic-v3: Assorted improvements Marc Zyngier
2022-04-05 18:38 ` Marc Zyngier [this message]
2022-04-05 18:38 ` [PATCH v2 2/3] irqchip/gic-v3: Detect LPI invalidation MMIO registers Marc Zyngier
2022-05-04 15:15 ` [irqchip: irq/irqchip-next] " irqchip-bot for Marc Zyngier
2022-04-05 18:38 ` [PATCH v2 3/3] irqchip/gic-v3: Relax polling of GIC{R,D}_CTLR.RWP Marc Zyngier
2022-05-04 15:15 ` [irqchip: irq/irqchip-next] " irqchip-bot for Marc Zyngier
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