From: Rob Clark <robdclark@gmail.com>
To: dri-devel@lists.freedesktop.org
Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org,
Rob Clark <robdclark@chromium.org>,
Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>,
Abhinav Kumar <quic_abhinavk@quicinc.com>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
Akhil P Oommen <quic_akhilpo@quicinc.com>,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Jonathan Marek <jonathan@marek.ca>,
Jordan Crouse <jordan@cosmicpenguin.net>,
linux-kernel@vger.kernel.org (open list)
Subject: [PATCH] drm/msm: Fix range size vs end confusion
Date: Thu, 7 Apr 2022 13:28:33 -0700 [thread overview]
Message-ID: <20220407202836.1211268-1-robdclark@gmail.com> (raw)
From: Rob Clark <robdclark@chromium.org>
The fourth param is size, rather than range_end.
Note that we could increase the address space size if we had a way to
prevent buffers from spanning a 4G split, mostly just to avoid fw bugs
with 64b math.
Fixes: 84c31ee16f90 ("drm/msm/a6xx: Add support for per-instance pagetables")
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 17de46fc4bf2..80d57608b34a 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1742,7 +1742,7 @@ a6xx_create_private_address_space(struct msm_gpu *gpu)
return ERR_CAST(mmu);
return msm_gem_address_space_create(mmu,
- "gpu", 0x100000000ULL, 0x1ffffffffULL);
+ "gpu", 0x100000000ULL, SZ_4G);
}
static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
--
2.35.1
next reply other threads:[~2022-04-07 20:40 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-07 20:28 Rob Clark [this message]
2022-04-08 12:21 ` [PATCH] drm/msm: Fix range size vs end confusion Dmitry Baryshkov
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