Re: [PATCH v3 15/15] coresight: etm4x: Cleanup TRCRSCTLRn register accesses

Mike Leach
2022-04-12T11:58:06Z

On Wed, 23 Mar 2022 at 16:15, Mathieu Poirier
<mathieu.poirier@linaro.org> wrote:
>
> On Fri, Mar 04, 2022 at 05:19:12PM +0000, James Clark wrote:
> > This is a no-op change for style and consistency and has no effect on
> > the binary output by the compiler. In sysreg.h fields are defined as
> > the register name followed by the field name and then _MASK. This
> > allows for grepping for fields by name rather than using magic numbers.
> >
> > Signed-off-by: James Clark <james.clark@arm.com>
> > ---
> > drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 7 +++++--
> > drivers/hwtracing/coresight/coresight-etm4x.h | 7 +++++++
> > 2 files changed, 12 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > index 3ae6f4432646..6ea8181816fc 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > @@ -1726,8 +1726,11 @@ static ssize_t res_ctrl_store(struct device *dev,
> > /* For odd idx pair inversal bit is RES0 */
> > if (idx % 2 != 0)
> > /* PAIRINV, bit[21] */
> > - val &= ~BIT(21);
> > - config->res_ctrl[idx] = val & GENMASK(21, 0);
> > + val &= ~TRCRSCTLRn_PAIRINV;
> > + config->res_ctrl[idx] = val & (TRCRSCTLRn_PAIRINV |
> > + TRCRSCTLRn_INV |
> > + TRCRSCTLRn_GROUP_MASK |
> > + TRCRSCTLRn_SELECT_MASK);
> > spin_unlock(&drvdata->spinlock);
> > return size;
> > }
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> > index 15704982357f..2c412841b126 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> > @@ -223,6 +223,13 @@
> > #define TRCBBCTLR_MODE BIT(8)
> > #define TRCBBCTLR_RANGE_MASK GENMASK(7, 0)
> >
> > +#define TRCRSCTLRn_PAIRINV BIT(21)
> > +#define TRCRSCTLRn_INV BIT(20)
> > +#define TRCRSCTLRn_GROUP_MASK GENMASK(19, 16)
> > +#define TRCRSCTLRn_SELECT_MASK GENMASK(15, 0)
> > +
> > +
> > +
>
> Two extra lines.
>
> > /*
> > * System instructions to access ETM registers.
> > * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions
> > --
> > 2.28.0
> >

Reviewed-by: Mike Leach <mike.leach@linaro.org>

--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK