From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4579AC433F5 for ; Sat, 16 Apr 2022 12:33:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231986AbiDPMgU (ORCPT ); Sat, 16 Apr 2022 08:36:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56192 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231607AbiDPMgI (ORCPT ); Sat, 16 Apr 2022 08:36:08 -0400 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 92655FE427 for ; Sat, 16 Apr 2022 05:33:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1650112417; x=1681648417; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bLV46reasuOPuFLE2C3UtgPLXAur55KabjsunKbN5r0=; b=Y8SRLd1Kkr4zOjjXAyGjvRdtMmYtSqspLagYFdqMrNFNNTjVPDPXNG3F kpOr4GqYtpXg/6A9qpjwM1jf//gc0QdH26nny8cYh/QErZE1/NpmJirvd hpeWQnUiE4AzxbxOOUHts8CfeVt4Es9+8Knl4hFnwgKKoAKgQdX5u/146 oSIVvgKSS+18geueBzfW+aA8PDua+FeWCyIQIEbnA59XGHnzqrFfKwkyh Al/SJlb6MJrKOOwsbb4a3oCqIV5tnvQs3EuI7USYU5Lmx9hvQUFG58D2V tdzr1ROLYYHeUFy19tIT6RGyH4kGRY1rlrksjNJTqxaCcisl482cTyWXk w==; X-IronPort-AV: E=McAfee;i="6400,9594,10318"; a="243221104" X-IronPort-AV: E=Sophos;i="5.90,264,1643702400"; d="scan'208";a="243221104" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2022 05:33:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,264,1643702400"; d="scan'208";a="701332481" Received: from allen-box.sh.intel.com ([10.239.159.48]) by fmsmga001.fm.intel.com with ESMTP; 16 Apr 2022 05:33:35 -0700 From: Lu Baolu To: Jacob jun Pan , Kevin Tian , Ashok Raj , Liu Yi L Cc: iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH 3/3] iommu/vt-d: Size Page Request Queue to avoid overflow condition Date: Sat, 16 Apr 2022 20:30:49 +0800 Message-Id: <20220416123049.879969-4-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220416123049.879969-1-baolu.lu@linux.intel.com> References: <20220416123049.879969-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org PRQ overflow may cause I/O throughput congestion, resulting in unnecessary degradation of IO performance. Appropriately increasing the length of PRQ can greatly reduce the occurrence of PRQ overflow. The count of maximum page requests that can be generated in parallel by a PCIe device is statically defined in the Outstanding Page Request Capacity field of the PCIe ATS configure space. The new lenght of PRQ is calculated by summing up the value of Outstanding Page Request Capacity register across all devices where Page Requests are supported on the real PR-capable platfrom (Intel Sapphire Rapids). The result is round to the nearest higher power of 2. The PRQ length is also double sized as the VT-d IOMMU driver only updates the Page Request Queue Head Register (PQH_REG) after processing the entire queue. Signed-off-by: Lu Baolu --- include/linux/intel-svm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/intel-svm.h b/include/linux/intel-svm.h index b3b125b332aa..207ef06ba3e1 100644 --- a/include/linux/intel-svm.h +++ b/include/linux/intel-svm.h @@ -9,7 +9,7 @@ #define __INTEL_SVM_H__ /* Page Request Queue depth */ -#define PRQ_ORDER 2 +#define PRQ_ORDER 4 #define PRQ_RING_MASK ((0x1000 << PRQ_ORDER) - 0x20) #define PRQ_DEPTH ((0x1000 << PRQ_ORDER) >> 5) -- 2.25.1