From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E087C433F5 for ; Mon, 18 Apr 2022 10:54:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235958AbiDRK4h (ORCPT ); Mon, 18 Apr 2022 06:56:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58224 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233434AbiDRK4b (ORCPT ); Mon, 18 Apr 2022 06:56:31 -0400 Received: from mail-pg1-x52b.google.com (mail-pg1-x52b.google.com [IPv6:2607:f8b0:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5805D1901D for ; Mon, 18 Apr 2022 03:53:53 -0700 (PDT) Received: by mail-pg1-x52b.google.com with SMTP id q19so18236757pgm.6 for ; Mon, 18 Apr 2022 03:53:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JPOgTx9pa9Jl4kAK/bdibs/Vyw7ywaqt4uScFzAp1mk=; b=XdbYHNbKszoQHDpOsRevhS9azun0X0ln0c3yD3qvnSvlgl9hVQvV4CK+KicTkLkS68 q9WQGtLEAtDlWwdUc55/h1pMGqCgBWn7L8/cHVtanzWm5Y06K1MhzHMqH1hkwKRe33qv /2yhTYdSz4f9yjpFRDpP2TYyLKWulNxBwHuePirXOiQdMF0QN/ggKtR9nzAmsIxaDbyd tjf1XTGJ3ff5NGBoex79YYK5Asi1w43ICmwMbfYUXmghgaRYAenrylFchNjlseDtsN3Y NoKeX1RonA238IIC3fCyZGkaiFBH6bJfp3o4ZAgW7/xH/5PrPjvdI0PZMQuHh1E0xwwl OSGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JPOgTx9pa9Jl4kAK/bdibs/Vyw7ywaqt4uScFzAp1mk=; b=bISWrtOwVaRCMXTgINEP4PtMkhR4E7FD1y6d5s9vsxwocM34u4k51b2KO4PnhTccvl Lz4WEpJXlu2j6nmjiTG1vWP0swZ/12W1Z5qs8QvnY9kdauoqnN9jrRcoG2PbaoAHqAFZ Gqq4iarWTPZzue+56kVVCvDzMfR++YE5ceiDzwxqeaDGQPogER4TX6V/rsjGGElkS3QT iJv7YOkZMCLRtH9/0KeXkqhwqxDqgWcRDe2oSPWJOlcrSC/9BJK2b0cKDutJ3w4bf1hR S9+QGxQJHBXEis2sdey+4WfSl7GJD4c0c0289C8LdhOmp3PjGfHSy64nLwBorcPkd4N5 ya/Q== X-Gm-Message-State: AOAM531CVRYxdpNh4jbbB+jYEqmJC1kahJiSvC2m4idhGEMI3ZVBTgLb l1b/rNSAPHGPCtxiSz+3jqBf4A== X-Google-Smtp-Source: ABdhPJwTsCSdB4EfMf4LGMF3YogsrK+jMFNEXT4Zp1iXaRS9ZGqtlUUpSl4jtHmmIOreJRB8BQlnTA== X-Received: by 2002:a05:6a00:891:b0:4fe:1262:9b4e with SMTP id q17-20020a056a00089100b004fe12629b4emr11499956pfj.21.1650279232849; Mon, 18 Apr 2022 03:53:52 -0700 (PDT) Received: from localhost.localdomain ([122.172.241.223]) by smtp.gmail.com with ESMTPSA id j13-20020a056a00130d00b004f1025a4361sm12986278pfu.202.2022.04.18.03.53.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Apr 2022 03:53:52 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v6 2/7] irqchip/riscv-intc: Allow drivers to directly discover INTC hwnode Date: Mon, 18 Apr 2022 16:23:00 +0530 Message-Id: <20220418105305.1196665-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220418105305.1196665-1-apatel@ventanamicro.com> References: <20220418105305.1196665-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Various RISC-V drivers (such as SBI IPI, SBI Timer, SBI PMU, and KVM RISC-V) don't have associated DT node but these drivers need standard per-CPU (local) interrupts defined by the RISC-V privileged specification. We add riscv_get_intc_hwnode() in arch/riscv which allows RISC-V drivers not having DT node to discover INTC hwnode which in-turn helps these drivers to map per-CPU (local) interrupts provided by the INTC driver. Signed-off-by: Anup Patel --- arch/riscv/include/asm/irq.h | 4 ++++ arch/riscv/kernel/irq.c | 18 ++++++++++++++++++ drivers/irqchip/irq-riscv-intc.c | 7 +++++++ 3 files changed, 29 insertions(+) diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h index e4c435509983..43b9ebfbd943 100644 --- a/arch/riscv/include/asm/irq.h +++ b/arch/riscv/include/asm/irq.h @@ -12,6 +12,10 @@ #include +void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void)); + +struct fwnode_handle *riscv_get_intc_hwnode(void); + extern void __init init_IRQ(void); #endif /* _ASM_RISCV_IRQ_H */ diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c index 7207fa08d78f..96d3171f0ca1 100644 --- a/arch/riscv/kernel/irq.c +++ b/arch/riscv/kernel/irq.c @@ -7,9 +7,27 @@ #include #include +#include +#include #include #include +static struct fwnode_handle *(*__get_intc_node)(void); + +void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void)) +{ + __get_intc_node = fn; +} + +struct fwnode_handle *riscv_get_intc_hwnode(void) +{ + if (__get_intc_node) + return __get_intc_node(); + + return NULL; +} +EXPORT_SYMBOL_GPL(riscv_get_intc_hwnode); + int arch_show_interrupts(struct seq_file *p, int prec) { show_ipi_stats(p, prec); diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index b65bd8878d4f..084793a57af8 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -92,6 +92,11 @@ static const struct irq_domain_ops riscv_intc_domain_ops = { .xlate = irq_domain_xlate_onecell, }; +static struct fwnode_handle *riscv_intc_hwnode(void) +{ + return intc_domain->fwnode; +} + static int __init riscv_intc_init(struct device_node *node, struct device_node *parent) { @@ -125,6 +130,8 @@ static int __init riscv_intc_init(struct device_node *node, return rc; } + riscv_set_intc_hwnode_fn(riscv_intc_hwnode); + cpuhp_setup_state(CPUHP_AP_IRQ_RISCV_STARTING, "irqchip/riscv/intc:starting", riscv_intc_cpu_starting, -- 2.25.1