From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4955C433EF for ; Mon, 25 Apr 2022 13:20:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241829AbiDYNXG (ORCPT ); Mon, 25 Apr 2022 09:23:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47448 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241959AbiDYNWf (ORCPT ); Mon, 25 Apr 2022 09:22:35 -0400 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 364FE19C1F for ; Mon, 25 Apr 2022 06:19:31 -0700 (PDT) Received: from fraeml708-chm.china.huawei.com (unknown [172.18.147.206]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4Kn5Bl72TYz682wj; Mon, 25 Apr 2022 21:16:47 +0800 (CST) Received: from lhreml710-chm.china.huawei.com (10.201.108.61) by fraeml708-chm.china.huawei.com (10.206.15.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Mon, 25 Apr 2022 15:19:28 +0200 Received: from localhost (10.202.226.42) by lhreml710-chm.china.huawei.com (10.201.108.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Mon, 25 Apr 2022 14:19:27 +0100 Date: Mon, 25 Apr 2022 14:19:26 +0100 From: Jonathan Cameron To: Qing Wang CC: Catalin Marinas , Will Deacon , Sudeep Holla , Greg Kroah-Hartman , "Rafael J. Wysocki" , , , , Subject: Re: [PATCH V2 0/2] Add complex scheduler level for arm64 Message-ID: <20220425141926.00004d2e@Huawei.com> In-Reply-To: <1650628289-67716-1-git-send-email-wangqing@vivo.com> References: <1650628289-67716-1-git-send-email-wangqing@vivo.com> Organization: Huawei Technologies Research and Development (UK) Ltd. X-Mailer: Claws Mail 4.0.0 (GTK+ 3.24.29; i686-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.202.226.42] X-ClientProxiedBy: lhreml728-chm.china.huawei.com (10.201.108.79) To lhreml710-chm.china.huawei.com (10.201.108.61) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 22 Apr 2022 04:51:24 -0700 Qing Wang wrote: > From: Wang Qing > > The DSU cluster supports blocks that are called complexes > which contain up to two cores of the same type and some shared logic, > which sharing some logic between the cores can make a complex area efficient. > Given the complex shares things like the SVE units (cortex a510)... Why not handle this as SMT? Seems like a blurred boundary between separate cores and SMT threads. I think we need to express and potentially take advantage of knowledge about what logic is being shared. Jonathan > Complex also can be considered as a shared cache group smaller > than cluster. > > This patch adds complex level for complexs by parsing cache topology > form DT. It will directly benefit a lot of workload which loves more > resources such as memory bandwidth, caches. > > Note this patch only handle the DT case. > > V2: > fix commit log and loop more > > wangqing (2): > arch_topology: support for describing cache topology from DT > arm64: Add complex scheduler level for arm64 > > arch/arm64/Kconfig | 13 ++++++++++ > arch/arm64/kernel/smp.c | 48 ++++++++++++++++++++++++++++++++++- > drivers/base/arch_topology.c | 47 +++++++++++++++++++++++++++++++++- > include/linux/arch_topology.h | 3 +++ > 4 files changed, 109 insertions(+), 2 deletions(-) >