[PATCH v3 2/8] dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support for r9a06g032

Herve Codina
2022-04-22T12:09:22Z

Add internal PCI bridge support for the r9a06g032 SOC. The Renesas
RZ/N1D (R9A06G032) internal PCI bridge is compatible with the one
present in the R-Car Gen2 family.
Compared to the R-Car Gen2 family, it needs three clocks instead of
one.

Signed-off-by: Herve Codina <herve.codina@bootlin.com>
---
.../bindings/pci/renesas,pci-rcar-gen2.yaml | 43 ++++++++++++++++---
1 file changed, 37 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
index 494eb975c146..c29c46533e1b 100644
--- a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
+++ b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
@@ -32,6 +32,10 @@ properties:
- renesas,pci-r8a7793 # R-Car M2-N
- renesas,pci-r8a7794 # R-Car E2
- const: renesas,pci-rcar-gen2 # R-Car Gen2 and RZ/G1
+ - items:
+ - enum:
+ - renesas,pci-r9a06g032 # RZ/N1D
+ - const: renesas,pci-rzn1 # RZ/N1

reg:
items:
@@ -41,13 +45,9 @@ properties:
interrupts:
maxItems: 1

- clocks:
- items:
- - description: Device clock
+ clocks: true

- clock-names:
- items:
- - const: pclk
+ clock-names: true

resets:
maxItems: 1
@@ -113,6 +113,37 @@ required:
- "#size-cells"
- "#interrupt-cells"

+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,pci-rzn1
+
+then:
+ properties:
+ clocks:
+ items:
+ - description: Internal bus clock (AHB) for HOST
+ - description: Internal bus clock (AHB) Power Management
+ - description: PCI clock for USB subsystem
+ clock-names:
+ items:
+ - const: hclk_usbh
+ - const: hclk_usbpm
+ - const: clk_pci_usb
+ required:
+ - clock-names
+
+else:
+ properties:
+ clocks:
+ items:
+ - description: Device clock
+ clock-names:
+ items:
+ - const: pclk
+
unevaluatedProperties: false

examples:
--
2.35.1