Re: [PATCH] x86: Implement Linear Address Masking support

Kirill A. Shutemov
2022-05-12T17:02:45Z

On Thu, May 12, 2022 at 01:01:07PM +0000, David Laight wrote:
> From: Kirill A. Shutemov
> > Sent: 11 May 2022 03:28
> >
> > Linear Address Masking feature makes CPU ignore some bits of the virtual
> > address. These bits can be used to encode metadata.
> >
> > The feature is enumerated with CPUID.(EAX=07H, ECX=01H):EAX.LAM[bit 26].
> >
> > CR3.LAM_U57[bit 62] allows to encode 6 bits of metadata in bits 62:57 of
> > user pointers.
> >
> > CR3.LAM_U48[bit 61] allows to encode 15 bits of metadata in bits 62:48
> > of user pointers.
> >
> > CR4.LAM_SUP[bit 28] allows to encode metadata of supervisor pointers.
> > If 5-level paging is in use, 6 bits of metadata can be encoded in 62:57.
> > For 4-level paging, 15 bits of metadata can be encoded in bits 62:48.
> >
> ...
> > +static vaddr clean_addr(CPUArchState *env, vaddr addr)
> > +{
> > + CPUClass *cc = CPU_GET_CLASS(env_cpu(env));
> > +
> > + if (cc->tcg_ops->do_clean_addr) {
> > + addr = cc->tcg_ops->do_clean_addr(env_cpu(env), addr);
>
> The performance of a conditional indirect call will be horrid.
> Over-engineered when there is only one possible function.

It is QEMU patch. As I mentioned in the cover letter, it was rejected by
upstream, but it is functional and can be used for testing before HW
arrived.

I may give it another try when I get time to look deeper at TCG.

--
Kirill A. Shutemov