Re: [PATCH 09/12] riscv: add RISC-V Svpbmt extension support

Philipp Tomsich
2022-05-16T09:09:48Z

On Mon, 16 May 2022 at 08:11, Christoph Hellwig <hch@lst.de> wrote:
>
> > +config RISCV_ISA_SVPBMT
> > + bool "SVPBMT extension support"
>
> I don't think this prompt is very useful as it doesn't describe
> what it does. But do we even want people to disable it as it is
> really essentially for a fully functioning kernel and a pity that
> it took RISC-V so long to get there?

Given that RISC-V is (in some ways) an ISA construction set, there
will be valid use cases for embedded users to disable this (e.g. if
they have their own non-standard way to configure these). So while
kernels for binary distributions (and desktop, server, or
general-purpose embedded) will always enable these, I would fully
expect some users to want to turn these off.

@Heiko: I would request that we have a longer help text on this, which
explains what it is and ends with the usual "When in doubt, say Y."

> > + depends on 64BIT && MMU
> > + select RISCV_ALTERNATIVE
> > + default y
> > + help
> > + Adds support to dynamically detect the presence of the SVPBMT extension
>
> overly long line here.
>
> > index 5f1046e82d9f..dbfcd9b72bd8 100644
> > --- a/arch/riscv/include/asm/errata_list.h
> > +++ b/arch/riscv/include/asm/errata_list.h
> > @@ -14,6 +14,9 @@
> > #define ERRATA_SIFIVE_NUMBER 2
> > #endif
> >
> > +#define CPUFEATURE_SVPBMT 0
> > +#define CPUFEATURE_NUMBER 1
>
> is errata_list.h really the right place for architectural features?
>
> Otherwise looks good:
>
> Reviewed-by: Christoph Hellwig <hch@lst.de>