[PATCH 02/13] dt-bindings: reset: Add MT6735 reset bindings

Yassine Oudjana
2022-05-04T12:32:24Z

Add reset definitions for Mediatek MT6735 resets provided by
infracfg and pericfg.

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
---
MAINTAINERS | 2 ++
.../reset/mediatek,mt6735-infracfg.h | 31 +++++++++++++++++++
.../reset/mediatek,mt6735-pericfg.h | 31 +++++++++++++++++++
3 files changed, 64 insertions(+)
create mode 100644 include/dt-bindings/reset/mediatek,mt6735-infracfg.h
create mode 100644 include/dt-bindings/reset/mediatek,mt6735-pericfg.h

diff --git a/MAINTAINERS b/MAINTAINERS
index e917039b9d8c..de15c3d50d2d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12446,6 +12446,8 @@ F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h
F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h
F: include/dt-bindings/clock/mediatek,mt6735-pericfg.h
F: include/dt-bindings/clock/mediatek,mt6735-topckgen.h
+F: include/dt-bindings/reset/mediatek,mt6735-infracfg.h
+F: include/dt-bindings/reset/mediatek,mt6735-pericfg.h

MEDIATEK MT76 WIRELESS LAN DRIVER
M: Felix Fietkau <nbd@nbd.name>
diff --git a/include/dt-bindings/reset/mediatek,mt6735-infracfg.h b/include/dt-bindings/reset/mediatek,mt6735-infracfg.h
new file mode 100644
index 000000000000..86448f946568
--- /dev/null
+++ b/include/dt-bindings/reset/mediatek,mt6735-infracfg.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_RST_MT6735_INFRACFG_H
+#define _DT_BINDINGS_RST_MT6735_INFRACFG_H
+
+#define EMI_REG_RST 0
+#define DRAMC0_AO_RST 1
+#define AP_CIRQ_EINT_RST 3
+#define APXGPT_RST 4
+#define SCPSYS_RST 5
+#define KP_RST 6
+#define PMIC_WRAP_RST 7
+#define CLDMA_AO_TOP_RST 8
+#define EMI_RST 16
+#define CCIF_RST 17
+#define DRAMC0_RST 18
+#define EMI_AO_REG_RST 19
+#define CCIF_AO_RST 20
+#define TRNG_RST 21
+#define SYS_CIRQ_RST 22
+#define GCE_RST 23
+#define MM_IOMMU_RST 24
+#define CCIF1_RST 25
+#define CLDMA_TOP_PD_RST 26
+#define CBIP_P2P_MFG 27
+#define CBIP_P2P_APMIXED 28
+#define CBIP_P2P_CKSYS 29
+#define CBIP_P2P_MIPI 30
+#define CBIP_P2P_DDRPHY 31
+
+#endif
diff --git a/include/dt-bindings/reset/mediatek,mt6735-pericfg.h b/include/dt-bindings/reset/mediatek,mt6735-pericfg.h
new file mode 100644
index 000000000000..6cdfaa7ddadf
--- /dev/null
+++ b/include/dt-bindings/reset/mediatek,mt6735-pericfg.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_RST_MT6735_PERICFG_H
+#define _DT_BINDINGS_RST_MT6735_PERICFG_H
+
+#define UART0_SW_RST 0
+#define UART1_SW_RST 1
+#define UART2_SW_RST 2
+#define UART3_SW_RST 3
+#define UART4_SW_RST 4
+#define BTIF_SW_RST 6
+#define DISP_PWM_SW_RST 7
+#define PWM_SW_RST 8
+#define AUXADC_SW_RST 10
+#define DMA_SW_RST 11
+#define IRDA_SW_RST 12
+#define IRTX_SW_RST 13
+#define THERM_SW_RST 16
+#define MSDC2_SW_RST 17
+#define MSDC3_SW_RST 17
+#define MSDC0_SW_RST 19
+#define MSDC1_SW_RST 20
+#define I2C0_SW_RST 22
+#define I2C1_SW_RST 23
+#define I2C2_SW_RST 24
+#define I2C3_SW_RST 25
+#define USB_SW_RST 28
+
+#define SPI0_SW_RST 33
+
+#endif
--
2.36.0