From: Jisheng Zhang <jszhang@kernel.org>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>, Arnd Bergmann <arnd@arndb.de>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH v4] riscv: add irq stack support
Date: Tue, 24 May 2022 23:39:28 +0800 [thread overview]
Message-ID: <20220524153928.2488-1-jszhang@kernel.org> (raw)
Currently, IRQs are still handled on the kernel stack of the current
task on riscv platforms. If the task has a deep call stack at the time
of interrupt, and handling the interrupt also requires a deep stack,
it's possible to see stack overflow.
Before this patch, the stack_max_size of a v5.17-rc1 kernel running on
a lichee RV board gave:
~ # cat /sys/kernel/debug/tracing/stack_max_size
3736
After this patch,
~ # cat /sys/kernel/debug/tracing/stack_max_size
3176
We reduce the max kernel stack usage by 560 bytes!
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
since v3:
- Always use vmalloc to allocate irq stack. Thank Arnd.
since v2:
- rebase on v5.18-rcN
- update commit msg, I.E remove the "it's possible to reduce the
THREAD_SIZE to 8KB for RV64 platforms..."
since v1:
- add __ro_after_init to the irq_stack[] array.
arch/riscv/include/asm/thread_info.h | 1 +
arch/riscv/kernel/asm-offsets.c | 2 ++
arch/riscv/kernel/entry.S | 33 +++++++++++++++++++++++++---
arch/riscv/kernel/irq.c | 12 ++++++++++
4 files changed, 45 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/include/asm/thread_info.h b/arch/riscv/include/asm/thread_info.h
index 74d888c8d631..98ea73721a0b 100644
--- a/arch/riscv/include/asm/thread_info.h
+++ b/arch/riscv/include/asm/thread_info.h
@@ -25,6 +25,7 @@
#endif
#define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER)
+#define IRQ_STACK_SIZE THREAD_SIZE
/*
* By aligning VMAP'd stacks to 2 * THREAD_SIZE, we can detect overflow by
* checking sp & (1 << THREAD_SHIFT), which we can do cheaply in the entry
diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offsets.c
index df9444397908..9e32748af0e8 100644
--- a/arch/riscv/kernel/asm-offsets.c
+++ b/arch/riscv/kernel/asm-offsets.c
@@ -37,6 +37,8 @@ void asm_offsets(void)
OFFSET(TASK_TI_PREEMPT_COUNT, task_struct, thread_info.preempt_count);
OFFSET(TASK_TI_KERNEL_SP, task_struct, thread_info.kernel_sp);
OFFSET(TASK_TI_USER_SP, task_struct, thread_info.user_sp);
+ OFFSET(TASK_TI_CPU, task_struct, thread_info.cpu);
+ OFFSET(TASK_STACK, task_struct, stack);
OFFSET(TASK_THREAD_F0, task_struct, thread.fstate.f[0]);
OFFSET(TASK_THREAD_F1, task_struct, thread.fstate.f[1]);
diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index c8b9ce274b9a..e91cae183ef4 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -126,12 +126,39 @@ skip_context_tracking:
*/
bge s4, zero, 1f
- la ra, ret_from_exception
+ /* preserve the sp */
+ move s0, sp
- /* Handle interrupts */
move a0, sp /* pt_regs */
+
+ /*
+ * Compare sp with the base of the task stack.
+ * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack,
+ * and should switch to the irq stack.
+ */
+ REG_L t0, TASK_STACK(tp)
+ xor t0, t0, s0
+ li t1, ~(THREAD_SIZE - 1)
+ and t0, t0, t1
+ bnez t0, 2f
+
+ la t1, irq_stack
+ REG_L t2, TASK_TI_CPU(tp)
+ slli t2, t2, RISCV_LGPTR
+ add t1, t1, t2
+ REG_L t2, 0(t1)
+ li t1, IRQ_STACK_SIZE
+ /* switch to the irq stack */
+ add sp, t2, t1
+
+2:
+ /* Handle interrupts */
la a1, generic_handle_arch_irq
- jr a1
+ jalr a1
+
+ /* Restore sp */
+ move sp, s0
+ j ret_from_exception
1:
/*
* Exceptions run with interrupts enabled or disabled depending on the
diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c
index 7207fa08d78f..6b26960e2e17 100644
--- a/arch/riscv/kernel/irq.c
+++ b/arch/riscv/kernel/irq.c
@@ -10,6 +10,8 @@
#include <linux/seq_file.h>
#include <asm/smp.h>
+void *irq_stack[NR_CPUS] __ro_after_init;
+
int arch_show_interrupts(struct seq_file *p, int prec)
{
show_ipi_stats(p, prec);
@@ -18,7 +20,17 @@ int arch_show_interrupts(struct seq_file *p, int prec)
void __init init_IRQ(void)
{
+ int cpu;
+
irqchip_init();
if (!handle_arch_irq)
panic("No interrupt controller found.");
+
+ for_each_possible_cpu(cpu) {
+ void *s = __vmalloc_node(IRQ_STACK_SIZE, THREAD_ALIGN,
+ THREADINFO_GFP, cpu_to_node(cpu),
+ __builtin_return_address(0));
+
+ irq_stack[cpu] = s;
+ }
}
--
2.34.1
reply other threads:[~2022-05-24 15:48 UTC|newest]
Thread overview: [no followups] expand[flat|nested] mbox.gz Atom feed
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220524153928.2488-1-jszhang@kernel.org \
--to=jszhang@kernel.org \
--cc=aou@eecs.berkeley.edu \
--cc=arnd@arndb.de \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox