From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8A2FC433F5 for ; Mon, 30 May 2022 14:14:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238964AbiE3OOt (ORCPT ); Mon, 30 May 2022 10:14:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54788 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239582AbiE3OJD (ORCPT ); Mon, 30 May 2022 10:09:03 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A9E7CFE28; Mon, 30 May 2022 06:42:41 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 828BB60F9E; Mon, 30 May 2022 13:42:30 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8BC79C3411F; Mon, 30 May 2022 13:42:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1653918150; bh=Xo83pvCZaeA+yRtlS2J30OFiQmLfqR0YGtYjdxcFqD0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dkQxYf/CpP/d/KBuwrG6nIPuR3atlMO46Rfrvt1Pzw37WiLIIEEzVAplDFO8ZXQMK H21UKPfiMRcO7b89r8bSae4KC2tvrGBjHe/YAKVsxlMAJu5kQf2i4VHlnJhcHC7boO jXTLjA3pUAQjZEWNoqJHfkBqJghHRA1o1W8CaCI8ONdq2OpmTkHIMbJVcVjP9fU3+E DW0Dp+kqW+Z0/mGy0lFPj54IC3q66Lq5JeTbJKN0lZeijgNn3O8rCF5MxJFC+C84B/ Oa5+ew+U9TDgE7Vlu812v70X4g10zIJaKy8GVOO7Wit5pRbwm+L/gR5YGy8wdLJyP6 f6eEIZazXTc3g== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Benjamin Gaignard , Ezequiel Garcia , Hans Verkuil , Mauro Carvalho Chehab , Sasha Levin , p.zabel@pengutronix.de, gregkh@linuxfoundation.org, linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-staging@lists.linux.dev Subject: [PATCH AUTOSEL 5.15 078/109] media: hantro: HEVC: unconditionnaly set pps_{cb/cr}_qp_offset values Date: Mon, 30 May 2022 09:37:54 -0400 Message-Id: <20220530133825.1933431-78-sashal@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220530133825.1933431-1-sashal@kernel.org> References: <20220530133825.1933431-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Benjamin Gaignard [ Upstream commit 46c836569196f377f87a3657b330cffaf94bd727 ] Always set pps_cb_qp_offset and pps_cr_qp_offset values in Hantro/G2 register whatever is V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT flag value. The vendor code does the same to set these values. This fixes conformance test CAINIT_G_SHARP_3. Fluster HEVC score is increase by one with this patch. Signed-off-by: Benjamin Gaignard Reviewed-by: Ezequiel Garcia Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Sasha Levin --- drivers/staging/media/hantro/hantro_g2_hevc_dec.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c index 340efb57fd18..ee069564205a 100644 --- a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c +++ b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c @@ -194,13 +194,8 @@ static void set_params(struct hantro_ctx *ctx) hantro_reg_write(vpu, &g2_max_cu_qpd_depth, 0); } - if (pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT) { - hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset); - hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset); - } else { - hantro_reg_write(vpu, &g2_cb_qp_offset, 0); - hantro_reg_write(vpu, &g2_cr_qp_offset, 0); - } + hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset); + hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset); hantro_reg_write(vpu, &g2_filt_offset_beta, pps->pps_beta_offset_div2); hantro_reg_write(vpu, &g2_filt_offset_tc, pps->pps_tc_offset_div2); -- 2.35.1