From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77C9BC4707F for ; Mon, 30 May 2022 14:23:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241421AbiE3OW5 (ORCPT ); Mon, 30 May 2022 10:22:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40156 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241102AbiE3ORO (ORCPT ); Mon, 30 May 2022 10:17:14 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3C66E110ACE; Mon, 30 May 2022 06:44:36 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 15E68B80D6B; Mon, 30 May 2022 13:44:32 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A0EC1C3411E; Mon, 30 May 2022 13:44:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1653918270; bh=Maymb1M0ojyJFMRqarHeva5kqwx2BGWP3YxckPlwec4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dg1DB0qc2/378gdwRyd4+HmebJF1xwlBrzWZlZYUJ+xlWcrk0q4W8nzyJj/nGbz8L qsZrX7R6Of7QWVS52kTdEcZXQsEUl8ijuDbkRCRbhiZEkDdNa39krrH/wwRmMOZt8B SXKW52DH7aPNIYH0snsPA1DC3pyt6q7gO7S7K5npPrCo2jQNXXdHmb+7MXLoDzAgrF lg7HXP7jW/O2+X2juj6DqK49PbU1LqZxs/193tRGsEn4bFc/Nkv0g1sgf/FEXaCP/8 3XbcPU1X3Q8aS/P3q7mV2/HM8JGCRYs2V6F6E1E4TVvtpL8LXG+hrT6uykRzIakIgO PCqRQG19XIo1Q== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Mike Travis , Steve Wahl , Borislav Petkov , Dimitri Sivanich , Thomas Gleixner , Sasha Levin , mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org Subject: [PATCH AUTOSEL 5.10 10/76] x86/platform/uv: Update TSC sync state for UV5 Date: Mon, 30 May 2022 09:43:00 -0400 Message-Id: <20220530134406.1934928-10-sashal@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220530134406.1934928-1-sashal@kernel.org> References: <20220530134406.1934928-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Mike Travis [ Upstream commit bb3ab81bdbd53f88f26ffabc9fb15bd8466486ec ] The UV5 platform synchronizes the TSCs among all chassis, and will not proceed to OS boot without achieving synchronization. Previous UV platforms provided a register indicating successful synchronization. This is no longer available on UV5. On this platform TSC_ADJUST should not be reset by the kernel. Signed-off-by: Mike Travis Signed-off-by: Steve Wahl Signed-off-by: Borislav Petkov Reviewed-by: Dimitri Sivanich Acked-by: Thomas Gleixner Link: https://lore.kernel.org/r/20220406195149.228164-3-steve.wahl@hpe.com Signed-off-by: Sasha Levin --- arch/x86/kernel/apic/x2apic_uv_x.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c index 40f466de8924..9c283562dfd4 100644 --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -199,7 +199,13 @@ static void __init uv_tsc_check_sync(void) int mmr_shift; char *state; - /* Different returns from different UV BIOS versions */ + /* UV5 guarantees synced TSCs; do not zero TSC_ADJUST */ + if (!is_uv(UV2|UV3|UV4)) { + mark_tsc_async_resets("UV5+"); + return; + } + + /* UV2,3,4, UV BIOS TSC sync state available */ mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR); mmr_shift = is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT; -- 2.35.1