From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F38F7C433EF for ; Wed, 1 Jun 2022 14:04:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354094AbiFAOEA (ORCPT ); Wed, 1 Jun 2022 10:04:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54840 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1354752AbiFAOAw (ORCPT ); Wed, 1 Jun 2022 10:00:52 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0C42D35AAF; Wed, 1 Jun 2022 06:57:17 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id A4A01615D2; Wed, 1 Jun 2022 13:56:43 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E856DC385A5; Wed, 1 Jun 2022 13:56:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1654091803; bh=0EBD0XpZZ+F2n0Cb3NfwT7URAxfSkcxQ+mqo9tvcibY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YRvyTRoVrz7x9pXsYEdWCh8d+JDjD4wLPaHsTBYJv58HAe25QMxbpKzZHPdoa9A8U tUoyvCm3NUCXJsX+A5ugeAG5PpskOIEe+EV8sNYSfoxuWuou7IQqyQiCq2R2EGMK54 0zDK/GLHQi9leOUTL7uqibG4xZaATjaIKQkMfrgcRJ1kRzR0eAMY5aHgGA93GCy1vs 3Yg7wusPmMABPaN7RSdi1CmeXbfjGlkLF1aiEOUphFy2vmVGnY2MPxaEqbBDCboIjK pxn0ihKsMCkKUvBr6+Y0ui21RrMHj2iwfmeixwDzPlJb2VKCEO3giu3du2UerthsQ3 yaKvy7UcZPUQg== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Marc Zyngier , Joey Gouly , Catalin Marinas , Sasha Levin , will@kernel.org, alexandru.elisei@arm.com, broonie@kernel.org, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH AUTOSEL 5.15 12/37] arm64: Expand ESR_ELx_WFx_ISS_TI to match its ARMv8.7 definition Date: Wed, 1 Jun 2022 09:55:57 -0400 Message-Id: <20220601135622.2003939-12-sashal@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220601135622.2003939-1-sashal@kernel.org> References: <20220601135622.2003939-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Marc Zyngier [ Upstream commit 6a437208cb942a2dd98f7e1c3fd347ed3d425ffc ] Starting with FEAT_WFXT in ARMv8.7, the TI field in the ISS that is reported on a WFx trap is expanded by one bit to allow the description of WFET and WFIT. Special care is taken to exclude the WFxT bit from the mask used to match WFI so that it also matches WFIT when trapped from EL0. Reviewed-by: Joey Gouly Signed-off-by: Marc Zyngier Acked-by: Catalin Marinas Link: https://lore.kernel.org/r/20220419182755.601427-2-maz@kernel.org Signed-off-by: Sasha Levin --- arch/arm64/include/asm/esr.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h index 8f59bbeba7a7..37bb84ea724d 100644 --- a/arch/arm64/include/asm/esr.h +++ b/arch/arm64/include/asm/esr.h @@ -133,7 +133,8 @@ #define ESR_ELx_CV (UL(1) << 24) #define ESR_ELx_COND_SHIFT (20) #define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT) -#define ESR_ELx_WFx_ISS_TI (UL(1) << 0) +#define ESR_ELx_WFx_ISS_TI (UL(3) << 0) +#define ESR_ELx_WFx_ISS_WFxT (UL(2) << 0) #define ESR_ELx_WFx_ISS_WFI (UL(0) << 0) #define ESR_ELx_WFx_ISS_WFE (UL(1) << 0) #define ESR_ELx_xVC_IMM_MASK ((1UL << 16) - 1) @@ -146,7 +147,8 @@ #define DISR_EL1_ESR_MASK (ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC) /* ESR value templates for specific events */ -#define ESR_ELx_WFx_MASK (ESR_ELx_EC_MASK | ESR_ELx_WFx_ISS_TI) +#define ESR_ELx_WFx_MASK (ESR_ELx_EC_MASK | \ + (ESR_ELx_WFx_ISS_TI & ~ESR_ELx_WFx_ISS_WFxT)) #define ESR_ELx_WFx_WFI_VAL ((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) | \ ESR_ELx_WFx_ISS_WFI) -- 2.35.1