From: Ravi Bangoria <ravi.bangoria@amd.com>
To: <acme@kernel.org>
Cc: <ravi.bangoria@amd.com>, <kan.liang@linux.intel.com>,
<namhyung@kernel.org>, <jolsa@kernel.org>, <irogers@google.com>,
<peterz@infradead.org>, <rrichter@amd.com>, <mingo@redhat.com>,
<mark.rutland@arm.com>, <tglx@linutronix.de>, <bp@alien8.de>,
<james.clark@arm.com>, <leo.yan@linaro.org>, <ak@linux.intel.com>,
<eranian@google.com>, <like.xu.linux@gmail.com>, <x86@kernel.org>,
<linux-perf-users@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <sandipan.das@amd.com>,
<ananth.narayan@amd.com>, <kim.phillips@amd.com>,
<santosh.shukla@amd.com>
Subject: [PATCH v6 1/8] perf record ibs: Warn about sampling period skew
Date: Sat, 4 Jun 2022 10:15:12 +0530 [thread overview]
Message-ID: <20220604044519.594-2-ravi.bangoria@amd.com> (raw)
In-Reply-To: <20220604044519.594-1-ravi.bangoria@amd.com>
Samples without an L3 miss are discarded and counter is reset with
random value (between 1-15 for fetch pmu and 1-127 for op pmu) when
IBS L3 miss filtering is enabled. This causes a sampling period skew
but there is no way to reconstruct aggregated sampling period. So
print a warning at perf record if user sets l3missonly=1.
Ex:
# perf record -c 10000 -C 0 -e ibs_op/l3missonly=1/
WARNING: Hw internally resets sampling period when L3 Miss Filtering is enabled
and tagged operation does not cause L3 Miss. This causes sampling period skew.
Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com>
Acked-by: Ian Rogers <irogers@google.com>
---
tools/perf/arch/x86/util/evsel.c | 52 ++++++++++++++++++++++++++++++++
tools/perf/util/evsel.c | 7 +++++
tools/perf/util/evsel.h | 1 +
3 files changed, 60 insertions(+)
diff --git a/tools/perf/arch/x86/util/evsel.c b/tools/perf/arch/x86/util/evsel.c
index 88306183d629..53763e583804 100644
--- a/tools/perf/arch/x86/util/evsel.c
+++ b/tools/perf/arch/x86/util/evsel.c
@@ -5,6 +5,10 @@
#include "util/env.h"
#include "util/pmu.h"
#include "linux/string.h"
+#include "util/debug.h"
+
+#define IBS_FETCH_L3MISSONLY (1ULL << 59)
+#define IBS_OP_L3MISSONLY (1ULL << 16)
void arch_evsel__set_sample_weight(struct evsel *evsel)
{
@@ -60,3 +64,51 @@ bool arch_evsel__must_be_in_group(const struct evsel *evsel)
(!strcasecmp(evsel->name, "slots") ||
strcasestr(evsel->name, "topdown"));
}
+
+static void ibs_l3miss_warn(void)
+{
+ pr_warning(
+"WARNING: Hw internally resets sampling period when L3 Miss Filtering is enabled\n"
+"and tagged operation does not cause L3 Miss. This causes sampling period skew.\n");
+}
+
+void arch__post_evsel_config(struct evsel *evsel, struct perf_event_attr *attr)
+{
+ struct perf_pmu *evsel_pmu, *ibs_fetch_pmu, *ibs_op_pmu;
+ static int warned_once;
+ /* 0: Uninitialized, 1: Yes, -1: No */
+ static int is_amd;
+
+ if (warned_once || is_amd == -1)
+ return;
+
+ if (!is_amd) {
+ struct perf_env *env = evsel__env(evsel);
+
+ if (!perf_env__cpuid(env) || !env->cpuid ||
+ !strstarts(env->cpuid, "AuthenticAMD")) {
+ is_amd = -1;
+ return;
+ }
+ is_amd = 1;
+ }
+
+ evsel_pmu = evsel__find_pmu(evsel);
+ if (!evsel_pmu)
+ return;
+
+ ibs_fetch_pmu = perf_pmu__find("ibs_fetch");
+ ibs_op_pmu = perf_pmu__find("ibs_op");
+
+ if (ibs_fetch_pmu && ibs_fetch_pmu->type == evsel_pmu->type) {
+ if (attr->config & IBS_FETCH_L3MISSONLY) {
+ ibs_l3miss_warn();
+ warned_once = 1;
+ }
+ } else if (ibs_op_pmu && ibs_op_pmu->type == evsel_pmu->type) {
+ if (attr->config & IBS_OP_L3MISSONLY) {
+ ibs_l3miss_warn();
+ warned_once = 1;
+ }
+ }
+}
diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c
index ce499c5da8d7..8fea51a9cd90 100644
--- a/tools/perf/util/evsel.c
+++ b/tools/perf/util/evsel.c
@@ -1091,6 +1091,11 @@ void __weak arch_evsel__fixup_new_cycles(struct perf_event_attr *attr __maybe_un
{
}
+void __weak arch__post_evsel_config(struct evsel *evsel __maybe_unused,
+ struct perf_event_attr *attr __maybe_unused)
+{
+}
+
static void evsel__set_default_freq_period(struct record_opts *opts,
struct perf_event_attr *attr)
{
@@ -1366,6 +1371,8 @@ void evsel__config(struct evsel *evsel, struct record_opts *opts,
*/
if (evsel__is_dummy_event(evsel))
evsel__reset_sample_bit(evsel, BRANCH_STACK);
+
+ arch__post_evsel_config(evsel, attr);
}
int evsel__set_filter(struct evsel *evsel, const char *filter)
diff --git a/tools/perf/util/evsel.h b/tools/perf/util/evsel.h
index 73ea48e94079..92bed8e2f7d8 100644
--- a/tools/perf/util/evsel.h
+++ b/tools/perf/util/evsel.h
@@ -297,6 +297,7 @@ void evsel__set_sample_id(struct evsel *evsel, bool use_sample_identifier);
void arch_evsel__set_sample_weight(struct evsel *evsel);
void arch_evsel__fixup_new_cycles(struct perf_event_attr *attr);
+void arch__post_evsel_config(struct evsel *evsel, struct perf_event_attr *attr);
int evsel__set_filter(struct evsel *evsel, const char *filter);
int evsel__append_tp_filter(struct evsel *evsel, const char *filter);
--
2.31.1
next prev parent reply other threads:[~2022-06-04 4:46 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-04 4:45 [PATCH v6 0/8] perf/amd: Zen4 IBS extensions support (tool changes) Ravi Bangoria
2022-06-04 4:45 ` Ravi Bangoria [this message]
2022-06-04 4:45 ` [PATCH v6 2/8] perf tool: Parse pmu caps sysfs only once Ravi Bangoria
2022-06-04 4:45 ` [PATCH v6 3/8] perf headers: Pass "cpu" pmu name while printing caps Ravi Bangoria
2022-06-04 4:45 ` [PATCH v6 4/8] perf headers: Store pmu caps in an array of strings Ravi Bangoria
2022-06-04 4:45 ` [PATCH v6 5/8] perf headers: Record non-cpu pmu capabilities Ravi Bangoria
2022-06-04 4:45 ` [PATCH v6 6/8] perf/x86/ibs: Add new IBS register bits into header Ravi Bangoria
2022-07-27 12:09 ` [tip: perf/core] " tip-bot2 for Ravi Bangoria
2022-06-04 4:45 ` [PATCH v6 7/8] perf tool ibs: Sync amd ibs header file Ravi Bangoria
2022-06-04 4:45 ` [PATCH v6 8/8] perf script ibs: Support new IBS bits in raw trace dump Ravi Bangoria
2022-06-06 23:46 ` [PATCH v6 0/8] perf/amd: Zen4 IBS extensions support (tool changes) Namhyung Kim
2022-06-24 16:19 ` Arnaldo Carvalho de Melo
2022-06-27 4:20 ` Ravi Bangoria
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