Re: [PATCH v2 2/5] dt-bindings: phy: Add ARTPEC-8 PCIe phy

Krzysztof Kozlowski
2022-06-06T10:15:57Z

On 03/06/2022 04:31, Wangseok Lee wrote:
> Add description to support Axis, ARTPEC-8 SoC.
> ARTPEC-8 is the SoC platform of Axis Communications
> and PCIe phy is designed based on SAMSUNG PHY.

This does not look like wrapped in Linux commit style.
https://elixir.bootlin.com/linux/v5.18-rc4/source/Documentation/process/submitting-patches.rst#L586

>
> changes since v1 :
> -'make dt_binding_check' result improvement
> -Add the missing property list
> -Align the indentation of continued lines/entries
>
> Signed-off-by: Wangseok Lee <wangseok.lee@samsung.com>
> ---
> .../bindings/phy/axis,artpec8-pcie-phy.yaml | 70 ++++++++++++++++++++++
> 1 file changed, 70 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml
> new file mode 100644
> index 0000000..ab9766f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml
> @@ -0,0 +1,70 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/axis,artpec8-pcie-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ARTPEC-8 SoC PCIe PHY Device Tree Bindings

Same comment as patch #1.

> +
> +maintainers:
> + - Jesper Nilsson <jesper.nilsson@axis.com>
> +
> +properties:
> + compatible:
> + const: axis,artpec8-pcie-phy
> +
> + reg:
> + items:
> + - description: PHY registers.
> + - description: PHY coding sublayer registers.
> +
> + reg-names:
> + items:
> + - const: phy
> + - const: pcs
> +
> + "#phy-cells":
> + const: 0
> +
> + clocks:
> + items:
> + - description: PCIe PHY reference clock
> +
> + clock-names:
> + items:
> + - const: ref_clk

Same comment as patch #1.

> +
> + num-lanes:
> + const: 2
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - "#phy-cells"
> + - clocks
> + - clock-names
> + - num-lanes
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + artpec8 {

Same comment as patch #1.

> + #address-cells = <2>;
> + #size-cells = <2>;
> + pcie_phy: pcie-phy@16c80000 {
> + compatible = "axis,artpec8-pcie-phy";
> + reg = <0x0 0x16c80000 0x0 0x2000>,
> + <0x0 0x16c90000 0x0 0x1000>;
> + reg-names = "phy", "pcs";
> + #phy-cells = <0>;
> + clocks = <&clock_cmu_fsys 53>;
> + clock-names = "ref_clk";
> + num-lanes = <2>;
> + };
> + };
> +...

Best regards,
Krzysztof