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From: Tinghan Shen <tinghan.shen@mediatek.com>
To: Bjorn Andersson <bjorn.andersson@linaro.org>,
	Mathieu Poirier <mathieu.poirier@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Lee Jones <lee.jones@linaro.org>,
	Benson Leung <bleung@chromium.org>,
	"Guenter Roeck" <groeck@chromium.org>,
	Sebastian Reichel <sebastian.reichel@collabora.com>,
	Daisuke Nojiri <dnojiri@chromium.org>,
	Kees Cook <keescook@chromium.org>,
	Tinghan Shen <tinghan.shen@mediatek.com>,
	"Gustavo A. R. Silva" <gustavoars@kernel.org>,
	Prashant Malani <pmalani@chromium.org>,
	Enric Balletbo i Serra <enric.balletbo@collabora.com>
Cc: <linux-remoteproc@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-mediatek@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <chrome-platform@lists.linux.dev>,
	<Project_Global_Chrome_Upstream_Group@mediatek.com>,
	<weishunc@google.com>
Subject: [PATCH v2 4/9] remoteproc: mediatek: Support probing for the 2nd core of dual-core SCP
Date: Wed, 8 Jun 2022 16:35:48 +0800	[thread overview]
Message-ID: <20220608083553.8697-5-tinghan.shen@mediatek.com> (raw)
In-Reply-To: <20220608083553.8697-1-tinghan.shen@mediatek.com>

The mtk_scp.c driver only supports the single core SCP and the
1st core of a dual-core SCP. This patch extends it for the 2nd core.

MT8195 SCP is a dual-core MCU. Both cores are housed in the same subsys.
They have the same viewpoint of registers and memory.

Core 1 of the SCP features its own set of core configuration registers,
interrupt controller, timers, and DMAs. The rest of the peripherals
in this subsystem are shared by core 0 and core 1.

As for memory, core 1 has its own cache memory. the SCP SRAM is shared
by core 0 and core 1.

Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
---
 drivers/remoteproc/mtk_scp.c | 22 ++++++++++++++++++++--
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c
index 3510c6d0bbc8..91b4aefde4ac 100644
--- a/drivers/remoteproc/mtk_scp.c
+++ b/drivers/remoteproc/mtk_scp.c
@@ -23,6 +23,10 @@
 #define MAX_CODE_SIZE 0x500000
 #define SECTION_NAME_IPI_BUFFER ".ipi_buffer"
 
+#define SCP_CORE_0 0
+#define SCP_CORE_1 1
+#define SCP_CORE_SINGLE 0xF
+
 /**
  * scp_get() - get a reference to SCP.
  *
@@ -836,6 +840,7 @@ static int scp_probe(struct platform_device *pdev)
 	struct resource *res;
 	const char *fw_name = "scp.img";
 	int ret, i;
+	u32 core_id = SCP_CORE_SINGLE;
 
 	ret = rproc_of_parse_firmware(dev, 0, &fw_name);
 	if (ret < 0 && ret != -EINVAL)
@@ -851,8 +856,16 @@ static int scp_probe(struct platform_device *pdev)
 	scp->data = of_device_get_match_data(dev);
 	platform_set_drvdata(pdev, scp);
 
+	ret = of_property_read_u32_index(dev->of_node, "mediatek,scp-core", 1, &core_id);
+	if (ret == 0)
+		dev_info(dev, "Boot SCP dual core %u\n", core_id);
+
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
-	scp->sram_base = devm_ioremap_resource(dev, res);
+	if (core_id == SCP_CORE_1)
+		scp->sram_base = devm_ioremap(dev, res->start, resource_size(res));
+	else
+		scp->sram_base = devm_ioremap_resource(dev, res);
+
 	if (IS_ERR(scp->sram_base))
 		return dev_err_probe(dev, PTR_ERR(scp->sram_base),
 				     "Failed to parse and map sram memory\n");
@@ -873,7 +886,12 @@ static int scp_probe(struct platform_device *pdev)
 		scp->l1tcm_phys = res->start;
 	}
 
-	scp->reg_base = devm_platform_ioremap_resource_byname(pdev, "cfg");
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
+	if (core_id == SCP_CORE_1)
+		scp->reg_base = devm_ioremap(dev, res->start, resource_size(res));
+	else
+		scp->reg_base = devm_ioremap_resource(dev, res);
+
 	if (IS_ERR(scp->reg_base))
 		return dev_err_probe(dev, PTR_ERR(scp->reg_base),
 				     "Failed to parse and map cfg memory\n");
-- 
2.18.0


  parent reply	other threads:[~2022-06-08  9:17 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-08  8:35 [PATCH v2 0/9] Add support for MT8195 SCP 2nd core Tinghan Shen
2022-06-08  8:35 ` [PATCH v2 1/9] dt-binding: remoteproc: mediatek: Support dual-core SCP Tinghan Shen
2022-06-09 20:51   ` Rob Herring
2022-06-08  8:35 ` [PATCH v2 2/9] remoteproc: mediatek: Support hanlding scp core 1 wdt timeout Tinghan Shen
2022-08-29 17:40   ` Mathieu Poirier
2022-09-08 10:38     ` Tinghan Shen
2022-06-08  8:35 ` [PATCH v2 3/9] remoteproc: mediatek: Add SCP core 1 register definitions Tinghan Shen
2022-08-29 17:46   ` Mathieu Poirier
2022-06-08  8:35 ` Tinghan Shen [this message]
2022-08-29 19:42   ` [PATCH v2 4/9] remoteproc: mediatek: Support probing for the 2nd core of dual-core SCP Mathieu Poirier
2022-09-08 11:17     ` Tinghan Shen
     [not found]       ` <CANLsYkx6kXk8u_ajFbnhdWTkZBLtrq_z02jryLBSVH0x--_ZFw@mail.gmail.com>
2022-09-16 11:59         ` TingHan Shen
2022-09-16 17:15           ` Mathieu Poirier
2022-09-19  9:46             ` TingHan Shen
2022-09-19 20:53               ` Mathieu Poirier
2022-09-23  7:12               ` Peng Fan
2022-06-08  8:35 ` [PATCH v2 5/9] remoteproc: mediatek: Add chip dependent operations for SCP core 1 Tinghan Shen
2022-06-08  8:35 ` [PATCH v2 6/9] remoteproc: mediatek: Add SCP core 1 SRAM offset Tinghan Shen
2022-06-08  8:35 ` [PATCH v2 7/9] remoteproc: mediatek: Add SCP core 1 as a rproc subdevice Tinghan Shen
2022-06-08  8:35 ` [PATCH v2 8/9] remoteproc: mediatek: Wait SCP core 1 probe done Tinghan Shen
2022-06-08  8:35 ` [PATCH v2 9/9] mfd: cros_ec: Add SCP core 1 as a new CrOS EC MCU Tinghan Shen
2022-06-09  5:45 ` [PATCH v2 0/9] Add support for MT8195 SCP 2nd core Tinghan Shen

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