[esmil:visionfive 50/54] drivers/soc/sifive/sifive_l2_cache.c:158:17: error: implicit declaration of function 'writeq'; did you mean 'writel'?

[kernel test robot <lkp@intel.com>]

tree:   https://github.com/esmil/linux visionfive
head:   906be7ef2fb9e2f1fcb740d3d506768cddfc52ca
commit: bfa9ff08405bc12ac52070caf85a017127c9ef23 [50/54] RISC-V: Enable SIFIVE_L2_FLUSH for StarFive SoCs
config: riscv-randconfig-c004-20220609 (https://download.01.org/0day-ci/archive/20220611/202206111753.evF6g3ot-lkp@intel.com/config)
compiler: riscv32-linux-gcc (GCC) 11.3.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/esmil/linux/commit/bfa9ff08405bc12ac52070caf85a017127c9ef23
        git remote add esmil https://github.com/esmil/linux
        git fetch --no-tags esmil visionfive
        git checkout bfa9ff08405bc12ac52070caf85a017127c9ef23
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.3.0 make.cross W=1 O=build_dir ARCH=riscv SHELL=/bin/bash

If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

   drivers/soc/sifive/sifive_l2_cache.c: In function 'sifive_l2_flush64_range':
>> drivers/soc/sifive/sifive_l2_cache.c:158:17: error: implicit declaration of function 'writeq'; did you mean 'writel'? [-Werror=implicit-function-declaration]
     158 |                 writeq(line, l2_base + SIFIVE_L2_FLUSH64);
         |                 ^~~~~~
         |                 writel
   cc1: some warnings being treated as errors


vim +158 drivers/soc/sifive/sifive_l2_cache.c

a967a289f16969 arch/riscv/mm/sifive_l2_cache.c      Yash Shah          2019-05-06  126  
1c9c971346b0ca drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  127  #ifdef CONFIG_SIFIVE_L2_FLUSH
1c9c971346b0ca drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  128  void sifive_l2_flush64_range(unsigned long start, unsigned long len)
1c9c971346b0ca drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  129  {
1c9c971346b0ca drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  130  	unsigned long line;
1c9c971346b0ca drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  131  
1c9c971346b0ca drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  132  	if(!l2_base) {
1c9c971346b0ca drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  133  		pr_warn("L2CACHE: base addr invalid, skipping flush\n");
1c9c971346b0ca drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  134  		return;
1c9c971346b0ca drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  135  	}
1c9c971346b0ca drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  136  
1c9c971346b0ca drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  137  	/* TODO: if (len == 0), skipping flush or going on? */
1c9c971346b0ca drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  138  	if(!len) {
1c9c971346b0ca drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  139  		pr_debug("L2CACHE: flush64 range @ 0x%lx(len:0)\n", start);
1c9c971346b0ca drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  140  		return;
1c9c971346b0ca drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  141  	}
1c9c971346b0ca drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  142  
716e7e2d5d69db drivers/soc/sifive/sifive_l2_cache.c Atish Patra        2021-06-12  143  	len = len + (start % SIFIVE_L2_FLUSH64_LINE_LEN);
716e7e2d5d69db drivers/soc/sifive/sifive_l2_cache.c Atish Patra        2021-06-12  144  	start = ALIGN_DOWN(start, SIFIVE_L2_FLUSH64_LINE_LEN);
716e7e2d5d69db drivers/soc/sifive/sifive_l2_cache.c Atish Patra        2021-06-12  145  
1c9c971346b0ca drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  146  	/* make sure the address is in the range */
1c9c971346b0ca drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  147  	if(start < CONFIG_SIFIVE_L2_FLUSH_START ||
1c9c971346b0ca drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  148  	   (start + len) > (CONFIG_SIFIVE_L2_FLUSH_START +
1c9c971346b0ca drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  149  			     CONFIG_SIFIVE_L2_FLUSH_SIZE)) {
085675aa07e095 drivers/soc/sifive/sifive_l2_cache.c Geert Uytterhoeven 2021-05-21  150  		WARN(1, "L2CACHE: flush64 out of range: %lx(%lx), skip flush\n",
1c9c971346b0ca drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  151  		     start, len);
1c9c971346b0ca drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  152  		return;
1c9c971346b0ca drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  153  	}
1c9c971346b0ca drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  154  
1c9c971346b0ca drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  155  	mb();	/* sync */
1c9c971346b0ca drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  156  	for (line = start; line < start + len;
1c9c971346b0ca drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  157  	     line += SIFIVE_L2_FLUSH64_LINE_LEN) {
1c9c971346b0ca drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08 @158  		writeq(line, l2_base + SIFIVE_L2_FLUSH64);
1c9c971346b0ca drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  159  		mb();
1c9c971346b0ca drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  160  	}
1c9c971346b0ca drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  161  }
1c9c971346b0ca drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  162  EXPORT_SYMBOL_GPL(sifive_l2_flush64_range);
1c9c971346b0ca drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  163  #endif
1c9c971346b0ca drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  164  

:::::: The code at line 158 was first introduced by commit
:::::: 1c9c971346b0ca811114ae00fce28cbf3c34232b sifive/sifive_l2_cache: Add sifive_l2_flush64_range function

:::::: TO: Tom <support@vamrs.com>
:::::: CC: Emil Renner Berthing <kernel@esmil.dk>

-- 
0-DAY CI Kernel Test Service
https://01.org/lkp