From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB58DCCA47B for ; Mon, 13 Jun 2022 20:57:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351491AbiFMU5n (ORCPT ); Mon, 13 Jun 2022 16:57:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36556 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352294AbiFMUyW (ORCPT ); Mon, 13 Jun 2022 16:54:22 -0400 Received: from mail-oa1-f48.google.com (mail-oa1-f48.google.com [209.85.160.48]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 261F82AE21; Mon, 13 Jun 2022 13:23:00 -0700 (PDT) Received: by mail-oa1-f48.google.com with SMTP id 586e51a60fabf-fe539f9afbso9904269fac.5; Mon, 13 Jun 2022 13:23:00 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=hQtdW3mNzOqqAz0EIGKInm9VroMOpphYtVs06PrJmgg=; b=sgWVxLxxBXD+0AClpuxc1bxB4LHbDwNmCNptgoJ+TE2iBMgj58gnu2+moAuzI0j+1b 9H67WcjRqwFE1si0Kq8C3fCgmPqLZwVG/xDOfjBeSIz5Je+1PcRyeyrWvdQJ4E2fRN6Q ZdB0nEFVG5PH0iH0VW/egDcppdTLnVQBmmiozxyuoiT4Z/oKQMyeMECeoXuSdl1Cqk22 gwfFu/6DV0pHWVfGPZDnIRD/i1QqcRyEVN7/uk+XVle9EWwiXsvQEuz4OtQ6b8kIpzjQ a7AITtbtscu11vY+xHVQOfPnxvkhb68hbnIPVhsK3I0ZjxupYWXVPFxx6tdXbdLcywhB TmMA== X-Gm-Message-State: AJIora/l4nlkCUuFDm8x6g1AxwnSbRrQiJmmKngzVDZvTbUApbB7OGU/ 0gRxOhgA+qrcfYmvlHEZxw== X-Google-Smtp-Source: AGRyM1vrWgRbbtIgkaNRth576iwAsSlwfWEsZWYqAZSEG7WmXUmtS7T2Ef2c7HYaOgH45FwPN+G1dA== X-Received: by 2002:a05:6870:c38c:b0:f1:ce0b:4dd3 with SMTP id g12-20020a056870c38c00b000f1ce0b4dd3mr349702oao.12.1655151779463; Mon, 13 Jun 2022 13:22:59 -0700 (PDT) Received: from robh.at.kernel.org ([2607:fb90:20d2:bb97:4381:7341:60ed:a4a1]) by smtp.gmail.com with ESMTPSA id e14-20020a056871044e00b000f3347daaa6sm4490557oag.9.2022.06.13.13.22.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jun 2022 13:22:59 -0700 (PDT) Received: (nullmailer pid 4178168 invoked by uid 1000); Mon, 13 Jun 2022 20:00:32 -0000 Date: Mon, 13 Jun 2022 14:00:32 -0600 From: Rob Herring To: Serge Semin Cc: Bjorn Helgaas , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Kishon Vijay Abraham I , Serge Semin , Alexey Malahov , Pavel Parkhomenko , Frank Li , Manivannan Sadhasivam , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 02/18] PCI: dwc: Add unroll iATU space support to the regions disable method Message-ID: <20220613200032.GA4174748-robh@kernel.org> References: <20220610082535.12802-1-Sergey.Semin@baikalelectronics.ru> <20220610082535.12802-3-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220610082535.12802-3-Sergey.Semin@baikalelectronics.ru> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jun 10, 2022 at 11:25:18AM +0300, Serge Semin wrote: > The dw_pcie_disable_atu() method was introduced in the commit f8aed6ec624f > ("PCI: dwc: designware: Add EP mode support"). Since then it hasn't > changed at all. For all that time the method has supported the viewport > version of the iATU CSRs only. Basically it works for the DW PCIe IP-cores > older than v4.80a since the newer controllers are equipped with the > unrolled iATU/eDMA space. It means the methods using it like > pci_epc_ops.clear_bar and pci_epc_ops.unmap_addr callbacks just don't work > correctly for the DW PCIe controllers with unrolled iATU CSRs. The same > concerns the dw_pcie_setup_rc() method, which disables the outbound iATU > entries before re-initializing them. > > So in order to fix the problems denoted above let's convert the > dw_pcie_disable_atu() method to disabling the iATU inbound and outbound > regions in the unrolled iATU CSRs in case the DW PCIe controller has been > synthesized with the ones support. The former semantics will be remained > for the controller having iATU mapped over the viewport. > > Fixes: f8aed6ec624f ("PCI: dwc: designware: Add EP mode support") > Signed-off-by: Serge Semin > Reviewed-by: Manivannan Sadhasivam > Tested-by: Manivannan Sadhasivam > > --- > > Changelog v3: > - Convert region variable type to u32 in order to fix the implicit type > conversion peculiarity. (@kbot) > --- > drivers/pci/controller/dwc/pcie-designware.c | 16 +++++++++++++--- > 1 file changed, 13 insertions(+), 3 deletions(-) Reviewed-by: Rob Herring