From: ira.weiny@intel.com
To: Dan Williams <dan.j.williams@intel.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Ira Weiny <ira.weiny@intel.com>, Lukas Wunner <lukas@wunner.de>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Dave Jiang <dave.jiang@intel.com>,
Ben Widawsky <bwidawsk@kernel.org>,
linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org,
linux-pci@vger.kernel.org
Subject: [PATCH V12 7/9] cxl/port: Introduce cxl_cdat_valid()
Date: Mon, 27 Jun 2022 21:15:25 -0700 [thread overview]
Message-ID: <20220628041527.742333-8-ira.weiny@intel.com> (raw)
In-Reply-To: <20220628041527.742333-1-ira.weiny@intel.com>
From: Ira Weiny <ira.weiny@intel.com>
The CDAT data is protected by a checksum and should be the proper
length.
Introduce cxl_cdat_valid() to validate the data. While at it check and
store the sequence number.
Signed-off-by: Ira Weiny <ira.weiny@intel.com>
---
Changes from V8
Move code to cxl/core/pci.c
Changes from V6
Change name to cxl_cdat_valid() as this validates all the CDAT
data not just the header
Add error and debug prints
Changes from V5
New patch, split out
Update cdat_hdr_valid()
Remove revision and cs field parsing
There is no point in these
Add seq check and debug print.
---
drivers/cxl/cdat.h | 2 ++
drivers/cxl/core/pci.c | 36 ++++++++++++++++++++++++++++++++++++
2 files changed, 38 insertions(+)
diff --git a/drivers/cxl/cdat.h b/drivers/cxl/cdat.h
index c6a48ab326bf..39eb561081f2 100644
--- a/drivers/cxl/cdat.h
+++ b/drivers/cxl/cdat.h
@@ -91,10 +91,12 @@
*
* @table: cache of CDAT table
* @length: length of cached CDAT table
+ * @seq: Last read Sequence number of the CDAT table
*/
struct cxl_cdat {
void *table;
size_t length;
+ u32 seq;
};
#endif /* !__CXL_CDAT_H__ */
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index 4bd479ec0253..6d775cc3dca1 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -532,6 +532,40 @@ static int cxl_cdat_get_length(struct device *dev,
return rc;
}
+static bool cxl_cdat_valid(struct device *dev, struct cxl_cdat *cdat)
+{
+ u32 *table = cdat->table;
+ u8 *data8 = cdat->table;
+ u32 length, seq;
+ u8 check;
+ int i;
+
+ length = FIELD_GET(CDAT_HEADER_DW0_LENGTH, table[0]);
+ if ((length < CDAT_HEADER_LENGTH_BYTES) || (length > cdat->length)) {
+ dev_err(dev, "CDAT Invalid length %u (%zu-%zu)\n", length,
+ CDAT_HEADER_LENGTH_BYTES, cdat->length);
+ return false;
+ }
+
+ for (check = 0, i = 0; i < length; i++)
+ check += data8[i];
+
+ dev_dbg(dev, "CDAT length %u CS %u\n", length, check);
+ if (check != 0) {
+ dev_err(dev, "CDAT Invalid checksum %u\n", check);
+ return false;
+ }
+
+ seq = FIELD_GET(CDAT_HEADER_DW3_SEQUENCE, table[3]);
+ /* Store the sequence for now. */
+ if (cdat->seq != seq) {
+ dev_info(dev, "CDAT seq change %x -> %x\n", cdat->seq, seq);
+ cdat->seq = seq;
+ }
+
+ return true;
+}
+
static int cxl_cdat_read_table(struct device *dev,
struct pci_doe_mb *cdat_mb,
struct cxl_cdat *cdat)
@@ -579,6 +613,8 @@ static int cxl_cdat_read_table(struct device *dev,
} while (entry_handle != CXL_DOE_TABLE_ACCESS_LAST_ENTRY);
+ if (!rc && !cxl_cdat_valid(dev, cdat))
+ return -EIO;
return rc;
}
--
2.35.3
next prev parent reply other threads:[~2022-06-28 4:16 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-28 4:15 [PATCH V12 0/9] CXL: Read CDAT and DSMAS data ira.weiny
2022-06-28 4:15 ` [PATCH V12 1/9] PCI: Add vendor ID for the PCI SIG ira.weiny
2022-06-28 4:15 ` [PATCH V12 2/9] PCI: Replace magic constant for PCI Sig Vendor ID ira.weiny
2022-06-28 4:15 ` [PATCH V12 3/9] PCI: Create PCIe library functions in support of DOE mailboxes ira.weiny
2022-06-28 14:16 ` Jonathan Cameron
2022-06-28 14:56 ` Bjorn Helgaas
2022-06-28 18:20 ` Ira Weiny
2022-06-29 14:09 ` Jonathan Cameron
2022-06-30 4:34 ` Ira Weiny
2022-06-30 15:25 ` Jonathan Cameron
2022-07-01 22:22 ` Ira Weiny
2022-07-04 6:45 ` Jonathan Cameron
2022-06-29 16:53 ` Ira Weiny
2022-06-28 14:38 ` Jonathan Cameron
2022-06-28 16:58 ` Ira Weiny
2022-06-28 4:15 ` [PATCH V12 4/9] cxl/pci: Create PCI DOE mailbox's for memory devices ira.weiny
2022-06-28 14:33 ` Jonathan Cameron
2022-06-30 5:32 ` Ira Weiny
2022-06-30 15:32 ` Jonathan Cameron
2022-06-30 16:14 ` Davidlohr Bueso
2022-07-01 19:52 ` Ira Weiny
2022-06-28 4:15 ` [PATCH V12 5/9] driver-core: Introduce BIN_ATTR_ADMIN_{RO,RW} ira.weiny
2022-06-28 6:06 ` Greg Kroah-Hartman
2022-06-28 16:42 ` Ira Weiny
2022-06-29 1:10 ` Bjorn Helgaas
2022-06-28 4:15 ` [PATCH V12 6/9] cxl/port: Read CDAT table ira.weiny
2022-06-28 14:47 ` Jonathan Cameron
2022-06-30 3:35 ` Ira Weiny
2022-06-30 15:45 ` Jonathan Cameron
2022-06-28 4:15 ` ira.weiny [this message]
2022-06-28 14:49 ` [PATCH V12 7/9] cxl/port: Introduce cxl_cdat_valid() Jonathan Cameron
2022-06-30 4:42 ` Ira Weiny
2022-06-28 4:15 ` [PATCH V12 8/9] cxl/port: Retry reading CDAT on failure ira.weiny
2022-06-28 14:57 ` Jonathan Cameron
2022-06-30 3:40 ` Ira Weiny
2022-06-28 4:15 ` [PATCH V12 9/9] cxl/port: Parse out DSMAS data from CDAT table ira.weiny
2022-06-28 15:00 ` Jonathan Cameron
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