Re: [PATCH v1 04/14] reset: add polarfire soc reset support

Conor.Dooley
2022-07-01T16:22:19Z

On 30/06/2022 17:20, Conor Dooley - M52691 wrote:
> On 30/06/2022 10:12, Philipp Zabel wrote:
>
> (This came to me oddly quoted, so I have fixed it myself)
>
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> Hi Conor,
>>>
>>> On Do, 2022-06-30 at 09:05 +0100, Conor Dooley wrote:
>>> Add support for the resets on Microchip's PolarFire SoC (MPFS).
>>> Reset control is a single register, wedged in between registers for
>>> clock control. To fit with existed DT etc, the reset controller is
>>>
>> existing ^
>>>
>>> created using the aux device framework & set up in the clock driver.
>>>
>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>> ---
>>> drivers/reset/Kconfig | 9 +++
>>> drivers/reset/Makefile | 2 +-
>>> drivers/reset/reset-mpfs.c | 145 +++++++++++++++++++++++++++++++++++++
>>> 3 files changed, 155 insertions(+), 1 deletion(-)
>>> create mode 100644 drivers/reset/reset-mpfs.c
>>>
>>> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
>>> index 93c8d07ee328..edf48951f763 100644
>>> --- a/drivers/reset/Kconfig
>>> +++ b/drivers/reset/Kconfig
>>> @@ -122,6 +122,15 @@ config RESET_MCHP_SPARX5
>>> help
>>> This driver supports switch core reset for the Microchip Sparx5 SoC.
>>>
>>>
>>> +config RESET_POLARFIRE_SOC
>>> + bool "Microchip PolarFire SoC (MPFS) Reset Driver"
>>> + depends on AUXILIARY_BUS && MCHP_CLK_MPFS
>>> + default MCHP_CLK_MPFS
>>> + help
>>> + This driver supports peripheral reset for the Microchip PolarFire SoC
>>> +
>>> + CONFIG_RESET_MPFS
>>>
>> This doesn't look intentional.
>
> Correct. I fixed it when rebasing on -next and forgot to re-fix it
> when I had to reset back to -rc2...
>
>>>
>>> +
>>> config RESET_MESON
>>> tristate "Meson Reset Driver"
>>> depends on ARCH_MESON || COMPILE_TEST
>>> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
>>> index a80a9c4008a7..5fac3a753858 100644
>>> --- a/drivers/reset/Makefile
>>> +++ b/drivers/reset/Makefile
>>> @@ -17,6 +17,7 @@ obj-$(CONFIG_RESET_K210) += reset-k210.o
>>> obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
>>> obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
>>> obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o
>>> +obj-$(CONFIG_RESET_POLARFIRE_SOC) += reset-mpfs.o
>>> obj-$(CONFIG_RESET_MESON) += reset-meson.o
>>> obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o
>>> obj-$(CONFIG_RESET_NPCM) += reset-npcm.o
>>> @@ -38,4 +39,3 @@ obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
>>> obj-$(CONFIG_RESET_UNIPHIER_GLUE) += reset-uniphier-glue.o
>>> obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o
>>> obj-$(CONFIG_ARCH_ZYNQMP) += reset-zynqmp.o
>>> -
>>> diff --git a/drivers/reset/reset-mpfs.c b/drivers/reset/reset-mpfs.c
>>> new file mode 100644
>>> index 000000000000..49c47a3e6c70
>>> --- /dev/null
>>> +++ b/drivers/reset/reset-mpfs.c
>>> @@ -0,0 +1,145 @@
>>> +// SPDX-License-Identifier: GPL-2.0-only
>>> +/*
>>> + * PolarFire SoC (MPFS) Peripheral Clock Reset Controller
>>> + *
>>> + * Author: Conor Dooley <conor.dooley@microchip.com>
>>> + * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries.
>>> + *
>>> + */
>>> +#include <linux/auxiliary_bus.h>
>>> +#include <linux/delay.h>
>>> +#include <linux/module.h>
>>> +#include <linux/platform_device.h>
>>> +#include <linux/reset-controller.h>
>>> +#include <dt-bindings/clock/microchip,mpfs-clock.h>
>>> +#include <soc/microchip/mpfs.h>
>>> +
>>> +/*
>>> + * The ENVM reset is the lowest bit in the register & I am using the CLK_FOO
>>> + * defines in the dt to make things easier to configure - so this is accounting
>>> + * for the offset of 3 there.
>>> + */
>>> +#define MPFS_PERIPH_OFFSET CLK_ENVM
>>> +#define MPFS_NUM_RESETS 30u
>>> +#define MPFS_SLEEP_MIN_US 100
>>> +#define MPFS_SLEEP_MAX_US 200
>>> +
>>> +/*
>>> + * Peripheral clock resets
>>> + */
>>> +
>>> +static int mpfs_assert(struct reset_controller_dev *rcdev, unsigned long id)
>>> +{
>>> + u32 reg;
>>> +
>>> + reg = mpfs_reset_read(rcdev->dev);
>>> + reg |= (1u << id);
>>> + mpfs_reset_write(rcdev->dev, reg);
>>
>> This is missing a spinlock to protect against concurrent read-modify-
>> writes.
>>>
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int mpfs_deassert(struct reset_controller_dev *rcdev, unsigned long id)
>>> +{
>>> + u32 reg, val;
>>> +
>>> + reg = mpfs_reset_read(rcdev->dev);
>>> + val = reg & ~(1u << id);
>>
>> You could use BIT(id) instead of (1u << id).
>>
>>> + mpfs_reset_write(rcdev->dev, val);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int mpfs_status(struct reset_controller_dev *rcdev, unsigned long id)
>>> +{
>>> + u32 reg = mpfs_reset_read(rcdev->dev);
>>> +
>>> + return (reg & (1u << id));
>>
>> Side note, this works because MPFS_NUM_RESETS makes sure the sign bit
>> is never hit.
>
> I can add a comment to that effect if you want?

I'm going to respin with the two net patches removed.
I'll operate on the assumption of adding a comment here...

>
>>>
>>> +}
>>> +
>>> +static int mpfs_reset(struct reset_controller_dev *rcdev, unsigned long id)
>>> +{
>>> + mpfs_assert(rcdev, id);
>>> +
>>> + usleep_range(MPFS_SLEEP_MIN_US, MPFS_SLEEP_MAX_US);
>>> +
>>> + mpfs_deassert(rcdev, id);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static const struct reset_control_ops mpfs_reset_ops = {
>>> + .reset = mpfs_reset,
>>> + .assert = mpfs_assert,
>>> + .deassert = mpfs_deassert,
>>> + .status = mpfs_status,
>>> +};
>>> +
>>> +static int mpfs_reset_xlate(struct reset_controller_dev *rcdev,
>>> + const struct of_phandle_args *reset_spec)
>>> +{
>>> + unsigned int index = reset_spec->args[0];
>>> +
>>> + /*
>>> + * CLK_RESERVED does not map to a clock, but it does map to a reset,
>>> + * so it has to be accounted for here. It is the reset for the fabric,
>>> + * so if this reset gets called - do not reset it.
>>> + */
>>> + if (index == CLK_RESERVED) {
>>> + dev_err(rcdev->dev, "Resetting the fabric is not supported\n");
>>> + return -EINVAL;
>>> + }
>>> +
>>> + if (index < MPFS_PERIPH_OFFSET || index >= (MPFS_PERIPH_OFFSET + rcdev->nr_resets)) {
>>> + dev_err(rcdev->dev, "Invalid reset index %u\n", reset_spec->args[0]);
>>
>> s/reset_spec->args[0]/index/
>>
>>> + return -EINVAL;
>>> + }
>>> +
>>> + return index - MPFS_PERIPH_OFFSET;
>>> +}
>>> +
>>> +static int mpfs_reset_probe(struct auxiliary_device *adev,
>>> + const struct auxiliary_device_id *id)
>>> +{
>>> + struct device *dev = &adev->dev;
>>> + struct reset_controller_dev *rcdev;
>>> + int ret;
>>> +
>>> + rcdev = devm_kzalloc(dev, sizeof(*rcdev), GFP_KERNEL);
>>> + if (!rcdev)
>>> + return -ENOMEM;
>>> +
>>> + rcdev->dev = dev;
>>> + rcdev->dev->parent = adev->dev.parent;
>>>
>>> s/adev->dev./dev->/
>>>
>>> + rcdev->ops = &mpfs_reset_ops;
>>> + rcdev->of_node = adev->dev.parent->of_node;
>>>
>>> s/adev->dev./dev->/
>>>
>>> + rcdev->of_reset_n_cells = 1;
>>> + rcdev->of_xlate = mpfs_reset_xlate;
>>> + rcdev->nr_resets = MPFS_NUM_RESETS;
>>> +
>>> + ret = devm_reset_controller_register(dev, rcdev);
>>> + if (!ret)
>>> + dev_info(dev, "Registered MPFS reset controller\n");
>>
>> Is this really useful information for most users?
>
> Probably not, but it is useful for my CI haha.
> If you don't like it, I will remove it.

...and removal here.
Thanks for your review Philipp :)
Conor.

>
>>
>>> +
>>> + return ret;
>>> +}
>>> +
>>> +static const struct auxiliary_device_id mpfs_reset_ids[] = {
>>> + {
>>> + .name = "clk_mpfs.reset-mpfs",
>>> + },
>>> + { }
>>> +};
>>> +MODULE_DEVICE_TABLE(auxiliary, mpfs_reset_ids);
>>> +
>>> +static struct auxiliary_driver mpfs_reset_driver = {
>>> + .probe = mpfs_reset_probe,
>>> + .id_table = mpfs_reset_ids,
>>> +};
>>> +
>>> +module_auxiliary_driver(mpfs_reset_driver);
>>> +
>>> +MODULE_DESCRIPTION("Microchip PolarFire SoC Reset Driver");
>>> +MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
>>> +MODULE_LICENSE("GPL");
>>> +MODULE_IMPORT_NS(MCHP_CLK_MPFS);
>>>
>> regards
>> Philipp