Re: [PATCH 0/7] phy: ti: phy-j721e-wiz: Add support for j7200-wiz-10g

Vinod Koul
2022-08-30T05:13:50Z

On 28-06-22, 15:22, Roger Quadros wrote:
> Hi,
>
> The SERDES in J7200 SR2.0 supports 2 reference clocks.
> The second reference clock (core_ref1_clk) is hardwired to
> MAIN_PLL3_HSDIV4_CLKOUT (100/125/156.25 MHz).
>
> Add a new compatible "j7200-wiz-10g" for this device.
>
> The external clocks to SERDES PLL refclock mapping is now
> controlled by a special register in System Control Module
> (SCM) space. Add a property "ti,scm" to reference it and
> configure it in the driver.

Applied, thanks

--
~Vinod