[PATCH 0/7] phy: ti: phy-j721e-wiz: Add support for j7200-wiz-10g

Roger Quadros
2022-06-28T12:23:21Z

Hi,

The SERDES in J7200 SR2.0 supports 2 reference clocks.
The second reference clock (core_ref1_clk) is hardwired to
MAIN_PLL3_HSDIV4_CLKOUT (100/125/156.25 MHz).

Add a new compatible "j7200-wiz-10g" for this device.

The external clocks to SERDES PLL refclock mapping is now
controlled by a special register in System Control Module
(SCM) space. Add a property "ti,scm" to reference it and
configure it in the driver.

cheers,
-roger

Roger Quadros (4):
dt-bindings: phy: ti,phy-j721e-wiz: deprecate clock MUX nodes
dt-bindings: phy: ti,phy-j721e-wiz: Add support for ti,j7200-wiz-10g
phy: ti: phy-j721e-wiz: add support for j7200-wiz-10g
phy: ti: phy-j721e-wiz: set PMA_CMN_REFCLK_DIG_DIV based on reflk rate

Siddharth Vadapalli (1):
phy: ti: phy-j721e-wiz: Add SGMII support in wiz driver for J7200

Swapnil Jakhade (1):
dt-bindings: phy: Add PHY_TYPE_USXGMII definition

Tanmay Patil (1):
phy: ti: phy-j721e-wiz.c: Add usxgmii support in wiz driver

.../bindings/phy/ti,phy-j721e-wiz.yaml | 24 +-
drivers/phy/ti/phy-j721e-wiz.c | 230 ++++++++++++++++--
include/dt-bindings/phy/phy.h | 1 +
3 files changed, 239 insertions(+), 16 deletions(-)

--
2.17.1