From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90B1DC43334 for ; Sat, 9 Jul 2022 08:57:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229555AbiGII51 (ORCPT ); Sat, 9 Jul 2022 04:57:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50770 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229471AbiGII5Z (ORCPT ); Sat, 9 Jul 2022 04:57:25 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2E0E357204 for ; Sat, 9 Jul 2022 01:57:25 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id CEB7BB800C1 for ; Sat, 9 Jul 2022 08:57:23 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 91E53C3411C; Sat, 9 Jul 2022 08:57:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1657357042; bh=WrK+932CnJxu9v8WAmxUaGWCfO5YJRZCEWjawDqYnT0=; h=From:To:Cc:Subject:Date:From; b=mKeXIv7o37yXwjHMETf9VMo+OdKNjBMlaziF3eTXegwp8iyRlMY82aBekCt1x3krB HCfnlt0NT2HuYIxSoyDVSBzkkZKi3n3SfjC1UBMV7pcCk0MtuQmchxb1G+4dGmIXYq upBHs5aar6mp6uwfhbzyuD+AEkYXK6ZO7rDdt+1balPmGlKjiXpSZuto4Cd+JnYh7J mV02M14kUsg4GmoOec2tI96vosRTsGgIE3zEZsmLKpdVmIC/dGVyp+kmneMJytUReq yxWVEPE+JIXV71VjsKnWdpWpOrUdym8RW3V39Skaql3rNPwj9qOtRXPCSnclRfFP/i 7aoVLck14g6qA== From: Jisheng Zhang To: Catalin Marinas , Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] arm64: save movk instructions in mov_q when the lower 16|32 bits are all zero Date: Sat, 9 Jul 2022 16:48:30 +0800 Message-Id: <20220709084830.3124-1-jszhang@kernel.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Currently mov_q is used to move a constant into a 64-bit register, when the lower 16 or 32bits of the constant are all zero, the mov_q emits one or two useless movk instructions. If the mov_q macro is used in hot code path, we want to save the movk instructions as much as possible. For example, when CONFIG_ARM64_MTE is 'Y' and CONFIG_KASAN_HW_TAGS is 'N', the following code in __cpu_setup() routine is the pontential optimization target: /* set the TCR_EL1 bits */ mov_q x10, TCR_MTE_FLAGS Before the patch: mov x10, #0x10000000000000 movk x10, #0x40, lsl #32 movk x10, #0x0, lsl #16 movk x10, #0x0 After the patch: mov x10, #0x10000000000000 movk x10, #0x40, lsl #32 Signed-off-by: Jisheng Zhang --- arch/arm64/include/asm/assembler.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index 8c5a61aeaf8e..09f408424cae 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -568,9 +568,13 @@ alternative_endif movz \reg, :abs_g3:\val movk \reg, :abs_g2_nc:\val .endif + .if ((((\val) >> 16) & 0xffff) != 0) movk \reg, :abs_g1_nc:\val .endif + .endif + .if (((\val) & 0xffff) != 0) movk \reg, :abs_g0_nc:\val + .endif .endm /* -- 2.34.1