From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21C75C43334 for ; Tue, 19 Jul 2022 12:51:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238373AbiGSMvY (ORCPT ); Tue, 19 Jul 2022 08:51:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52196 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242225AbiGSMtz (ORCPT ); Tue, 19 Jul 2022 08:49:55 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C91CE43315; Tue, 19 Jul 2022 05:19:54 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 1502EB81B10; Tue, 19 Jul 2022 12:19:52 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 753D7C341C6; Tue, 19 Jul 2022 12:19:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1658233190; bh=svGjCciLe2V3mMCFmTerpL7i6k7+OeAHHrb161NsqsQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=1h6r78PNyQytGLOGvwQpIOqmNmkejbnP0tABapufkYHKhAvRa2UPKflXajJCZU+SZ jzMH2a0Taje1ufQVZzbSt8MHtF2AzTWDxSHzKxIUnJ4VslhA7VJQdAkfLE2e6C7v+j 5gxLh/8aCCaTe0m55X9rgOu0T/g2/S4MNcqOYz3A= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Sudeep Holla , Daire McNamara , Conor Dooley , Sasha Levin Subject: [PATCH 5.18 038/231] riscv: dts: microchip: hook up the mpfs l2cache Date: Tue, 19 Jul 2022 13:52:03 +0200 Message-Id: <20220719114717.386407986@linuxfoundation.org> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220719114714.247441733@linuxfoundation.org> References: <20220719114714.247441733@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Conor Dooley [ Upstream commit efa310ba00716d7a872bdc5fa1f5545edc9efd69 ] The initial PolarFire SoC devicetree must have been forked off from the fu540 one prior to the addition of l2cache controller support being added there. When the controller node was added to mpfs.dtsi, it was not hooked up to the CPUs & thus sysfs reports an incorrect cache configuration. Hook it up. Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board") Reviewed-by: Sudeep Holla Reviewed-by: Daire McNamara Signed-off-by: Conor Dooley Signed-off-by: Sasha Levin --- arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi index f44fce1fe080..2f75e39d2fdd 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -51,6 +51,7 @@ cpu1: cpu@1 { riscv,isa = "rv64imafdc"; clocks = <&clkcfg CLK_CPU>; tlb-split; + next-level-cache = <&cctrllr>; status = "okay"; cpu1_intc: interrupt-controller { @@ -78,6 +79,7 @@ cpu2: cpu@2 { riscv,isa = "rv64imafdc"; clocks = <&clkcfg CLK_CPU>; tlb-split; + next-level-cache = <&cctrllr>; status = "okay"; cpu2_intc: interrupt-controller { @@ -105,6 +107,7 @@ cpu3: cpu@3 { riscv,isa = "rv64imafdc"; clocks = <&clkcfg CLK_CPU>; tlb-split; + next-level-cache = <&cctrllr>; status = "okay"; cpu3_intc: interrupt-controller { @@ -132,6 +135,7 @@ cpu4: cpu@4 { riscv,isa = "rv64imafdc"; clocks = <&clkcfg CLK_CPU>; tlb-split; + next-level-cache = <&cctrllr>; status = "okay"; cpu4_intc: interrupt-controller { #interrupt-cells = <1>; -- 2.35.1