From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C79B6C00144 for ; Fri, 29 Jul 2022 17:18:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238306AbiG2RSe (ORCPT ); Fri, 29 Jul 2022 13:18:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36468 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234120AbiG2RSa (ORCPT ); Fri, 29 Jul 2022 13:18:30 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F109381489; Fri, 29 Jul 2022 10:18:29 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id A6409B828C5; Fri, 29 Jul 2022 17:18:28 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E7C15C433C1; Fri, 29 Jul 2022 17:18:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1659115107; bh=e2HT1ixOuJoMonAGRNwr4kq3x5uFCATLmS986J+K4m8=; h=Date:From:To:Cc:Subject:In-Reply-To:From; b=N4/Ovl3eVPp1FDYa5h1Ucx7QhWp9a8MJWxt1TzfWEQnnp3hmh8UVT7XtndgTbXUoz tR3iaeYkjB9DNIxgz+msU6R8Wuw17Sxxg/CzJUdUZbDMXcDVkLyKu2BmXyh1ROOGYA 3OAW46UBhYsAvSH386Iwzs1xxRSx7jOgvzsdHBLI8ALWMU3jO7ID2/lxnE0HPPfPCK 5Cq77PztEvAL2CZJ3EH7e8X2UPumz+O1t/b2wGStWURZXr1C/Kef5BR6tIarlaW3iQ KT10UVBTBzT0s6O6oUKgKLgVb4ualYaeTqx4jHkQx/M9Boi0nRJQG2xOW3HiSjwcoi sZ9wilDCPE1sw== Date: Fri, 29 Jul 2022 12:18:25 -0500 From: Bjorn Helgaas To: Krishna chaitanya chundru Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, mka@chromium.org, quic_vbadigan@quicinc.com, quic_hemantk@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, quic_ramkri@quicinc.com, manivannan.sadhasivam@linaro.org, swboyd@chromium.org, dmitry.baryshkov@linaro.org, Stanimir Varbanov , Andy Gross , Bjorn Andersson , Lorenzo Pieralisi , Rob Herring , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Bjorn Helgaas Subject: Re: [PATCH v3] PCI: qcom: Allow L1 and its sub states Message-ID: <20220729171825.GA465668@bhelgaas> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1657886366-32685-1-git-send-email-quic_krichai@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jul 15, 2022 at 05:29:25PM +0530, Krishna chaitanya chundru wrote: > Allow L1 and its sub-states in the qcom pcie driver. > By default this is disabled in the qcom specific hardware. > So enabling it explicitly only for controllers belonging to > 2_7_0. > > This patch will not affect any link capability registers, this > will allow the link transitions to L1 and its sub states only > if they are already supported. > > Signed-off-by: Krishna chaitanya chundru > Reviewed-by: Manivannan Sadhasivam Applied to pci/ctrl/qcom for v5.20, thanks! > ---- > > Changes since v1 & v2: > - Update in the commit text only. > --- > drivers/pci/controller/dwc/pcie-qcom.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index a7202f0..5ef444f 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -41,6 +41,9 @@ > #define L23_CLK_RMV_DIS BIT(2) > #define L1_CLK_RMV_DIS BIT(1) > > +#define PCIE20_PARF_PM_CTRL 0x20 > +#define REQ_NOT_ENTR_L1 BIT(5) > + > #define PCIE20_PARF_PHY_CTRL 0x40 > #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16) > #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16) > @@ -1261,6 +1264,11 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) > val |= BIT(4); > writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); > > + /* Enable L1 and L1ss */ > + val = readl(pcie->parf + PCIE20_PARF_PM_CTRL); > + val &= ~REQ_NOT_ENTR_L1; > + writel(val, pcie->parf + PCIE20_PARF_PM_CTRL); > + > if (IS_ENABLED(CONFIG_PCI_MSI)) { > val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); > val |= BIT(31); > -- > 2.7.4 >