From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5BD4C25B0F for ; Thu, 11 Aug 2022 16:14:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236004AbiHKQOF (ORCPT ); Thu, 11 Aug 2022 12:14:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47072 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236303AbiHKQNF (ORCPT ); Thu, 11 Aug 2022 12:13:05 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8FAB0A8CCF; Thu, 11 Aug 2022 08:57:47 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 2D57261316; Thu, 11 Aug 2022 15:57:47 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 97065C433D6; Thu, 11 Aug 2022 15:57:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1660233466; bh=X4UDxapG/J4HmTp8WINo7LOgxjjfKDLoP8kY1Tp1qxo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cTfw0Xe+yWyd8ZWjKXKgjLuaupukUMNU3LQNZJ9K7wKZ9f449SOBavOMFcmX54SzI /whPJ5rXG62COGTtQCADTBlhTx7y/IHgORXeApQ7sT8trRoHGyW5AoDRJE635U9Qig Kp3TeSedQ7pTJZHUh1v24bpue+ZnQuTkk6PXtpV8TPH182BBcGZniFo6zTvk7OVfhY NLs8EmTGA/HErMKn0c8dvzU3p8AxoVTbmyOe4DK6ifyXy5Ct0S39Ngk1PZqbN5KvDw SXE0Yijz1DQJBmCqLnqlWAA1fh6spfFq0Qi09JU3ULJjkLJff62ISfFyqqSiH8rMRO JHpgf6+pNC4pg== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: David Zhang , Leo Li , Harry Wentland , Alex Deucher , Sasha Levin , Rodrigo.Siqueira@amd.com, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@linux.ie, daniel@ffwll.ch, Jerry.Zuo@amd.com, nicholas.kazlauskas@amd.com, mikita.lipski@amd.com, dale.zhao@amd.com, wenjing.liu@amd.com, Anthony.Koo@amd.com, agustin.gutierrez@amd.com, Anson.Jacob@amd.com, po-tchen@amd.com, rdunlap@infradead.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH AUTOSEL 5.15 11/69] drm/amd/display: fix system hang when PSR exits Date: Thu, 11 Aug 2022 11:55:20 -0400 Message-Id: <20220811155632.1536867-11-sashal@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220811155632.1536867-1-sashal@kernel.org> References: <20220811155632.1536867-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: David Zhang [ Upstream commit 6cc5c77300afbb285c4f41e04f3435ae3c484c40 ] [why] When DC driver send PSR exit dmub command to DMUB FW, it might not wait until PSR exit. Then it may hit the following deadlock situation. 1. DC driver send HW LOCK command to DMUB FW due to frame update 2. DMUB FW Set the HW lock 3. DMUB execute PSR exit sequence and stuck at polling DPG Pending register due to the HW Lock is set 4. DC driver ask DMUB FW to unlock HW lock, but DMUB FW is polling DPG pending register [how] The reason why DC driver doesn't wait until PSR exit is because some of the PSR state machine state is not update the dc driver. So when DC driver read back the PSR state, it take the state for PSR inactive. Signed-off-by: David Zhang Acked-by: Leo Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/display/dc/dc_types.h | 7 +++++++ drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 16 ++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index c1532930169b..ac8442f6f4da 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -639,10 +639,17 @@ enum dc_psr_state { PSR_STATE4b, PSR_STATE4c, PSR_STATE4d, + PSR_STATE4_FULL_FRAME, + PSR_STATE4a_FULL_FRAME, + PSR_STATE4b_FULL_FRAME, + PSR_STATE4c_FULL_FRAME, + PSR_STATE4_FULL_FRAME_POWERUP, PSR_STATE5, PSR_STATE5a, PSR_STATE5b, PSR_STATE5c, + PSR_STATE_HWLOCK_MGR, + PSR_STATE_POLLVUPDATE, PSR_STATE_INVALID = 0xFF }; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c index aa8403bc4c83..0dac025f8f02 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c @@ -72,6 +72,22 @@ static enum dc_psr_state convert_psr_state(uint32_t raw_state) state = PSR_STATE5b; else if (raw_state == 0x53) state = PSR_STATE5c; + else if (raw_state == 0x4A) + state = PSR_STATE4_FULL_FRAME; + else if (raw_state == 0x4B) + state = PSR_STATE4a_FULL_FRAME; + else if (raw_state == 0x4C) + state = PSR_STATE4b_FULL_FRAME; + else if (raw_state == 0x4D) + state = PSR_STATE4c_FULL_FRAME; + else if (raw_state == 0x4E) + state = PSR_STATE4_FULL_FRAME_POWERUP; + else if (raw_state == 0x60) + state = PSR_STATE_HWLOCK_MGR; + else if (raw_state == 0x61) + state = PSR_STATE_POLLVUPDATE; + else + state = PSR_STATE_INVALID; return state; } -- 2.35.1