[PATCH 5.18 0680/1095] clk: imx: clk-fracn-gppll: correct rdiv

Greg Kroah-Hartman
2022-08-15T21:48:06Z

From: Peng Fan <peng.fan@nxp.com>

[ Upstream commit f300cb7fccf69ba1835b983c76d70deb818ad194 ]

According to Reference Manual:
000b - Divide by 1
001b - Divide by 1
010b - Divide by 2
011b - Divide by 3
100b - Divide by 4
101b - Divide by 5
110b - Divide by 6
111b - Divide by 7

So only need increase rdiv by 1 when the register value is 0.

Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20220609132902.3504651-7-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/clk/imx/clk-fracn-gppll.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c
index cb06b0045e9e..025b73229cdd 100644
--- a/drivers/clk/imx/clk-fracn-gppll.c
+++ b/drivers/clk/imx/clk-fracn-gppll.c
@@ -149,7 +149,8 @@ static unsigned long clk_fracn_gppll_recalc_rate(struct clk_hw *hw, unsigned lon
if (rate)
return (unsigned long)rate;

- rdiv = rdiv + 1;
+ if (!rdiv)
+ rdiv = rdiv + 1;

switch (odiv) {
case 0:
--
2.35.1