From: Jacob Pan <jacob.jun.pan@linux.intel.com>
To: LKML <linux-kernel@vger.kernel.org>,
iommu@lists.linux.dev, x86@kernel.org,
Joerg Roedel <joro@8bytes.org>,
"Lu Baolu" <baolu.lu@linux.intel.com>
Cc: Raj Ashok <ashok.raj@intel.com>,
Thomas Gleixner <tglx@linutronix.de>,
Dave Hansen <dave.hansen@intel.com>,
"Borislav Petkov" <bp@alien8.de>,
"Ingo Molnar" <mingo@redhat.com>,
"Tian, Kevin" <kevin.tian@intel.com>, Yi Liu <yi.l.liu@intel.com>,
Jacob Pan <jacob.jun.pan@linux.intel.com>
Subject: [PATCH 0/2] Use the correct page tables for SVA under PTI
Date: Mon, 22 Aug 2022 13:12:11 -0700 [thread overview]
Message-ID: <20220822201213.352289-1-jacob.jun.pan@linux.intel.com> (raw)
Shared virtual addressing allows DMA to user virtual address, But the
x86 IOMMU drivers are using the kernel copy of the process page tables
when PTI is enabled. This patchset tightens the security intended by
PTI by performing SVA binding with the appropriate process PGDs.
I have tested on Intel platform only, would appreciate itif someone
could help with testing SVA-KPTI on an AMD system.
Jacob Pan (2):
x86: mm: Allow PTI helpers to be used outside x86/mm
iommu: Use the user PGD for SVA if PTI is enabled
arch/x86/include/asm/pgtable.h | 5 +++++
drivers/iommu/amd/iommu_v2.c | 4 +++-
drivers/iommu/intel/svm.c | 5 ++++-
3 files changed, 12 insertions(+), 2 deletions(-)
--
2.25.1
next reply other threads:[~2022-08-22 20:09 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-22 20:12 Jacob Pan [this message]
2022-08-22 20:12 ` [PATCH 1/2] x86: mm: Allow PTI helpers to be used outside x86/mm Jacob Pan
2022-08-22 20:12 ` [PATCH 2/2] iommu: Use the user PGD for SVA if PTI is enabled Jacob Pan
2022-08-22 22:31 ` Dave Hansen
2022-08-22 23:24 ` Jacob Pan
2022-08-22 23:25 ` Dave Hansen
2022-08-31 0:57 ` Baolu Lu
2022-08-30 17:08 ` [PATCH 0/2] Use the correct page tables for SVA under PTI Jacob Pan
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