From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B27B5C04AA5 for ; Thu, 25 Aug 2022 01:46:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234297AbiHYBqc (ORCPT ); Wed, 24 Aug 2022 21:46:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39742 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234992AbiHYBov (ORCPT ); Wed, 24 Aug 2022 21:44:51 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 279A79DFBB; Wed, 24 Aug 2022 18:40:05 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id E8BA0B826EB; Thu, 25 Aug 2022 01:39:55 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 60D44C433B5; Thu, 25 Aug 2022 01:39:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1661391594; bh=cWtP4DjNF9uuGOFmJLowltSk4Vz/PPcG3NBhgTmkfsA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=R/ITFKDPW0oawaZBKDQH5OEzzSBCh00ksyb10VmBC++jKVReKJ/mlYRxzhFqcFNkL 6cgnYglsh9tCZ6x/Wj8GawGjKlc3x20BVlPDrFfGEgH2w8zgCZZ8MWQIBiJzlEs/yc WEbgI5ZTAnfgFgYvjzTmDPVyf9JRIot0HO40F4h7C/wY4oqqtvZHu0pCpNutGU47rD tl6DnaqfYPFEJa4q0DFOtpfvMzN21ol8W53Fr0cJDxpPXtedshAwQqhNUfe/bfyjB9 qulXAokFKZgVuXKapAUbfxplLDd2KtnBL2zfeMmFyky7HTSRzoDo+gyKo+wTzFURMF io1l/+m7NrpdQ== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Ilya Bakoulin , Aric Cyr , Brian Chang , Daniel Wheeler , Alex Deucher , Sasha Levin , harry.wentland@amd.com, sunpeng.li@amd.com, Rodrigo.Siqueira@amd.com, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@linux.ie, daniel@ffwll.ch, HaoPing.Liu@amd.com, alex.hung@amd.com, Hansen.Dsouza@amd.com, dillon.varone@amd.com, baihaowen@meizu.com, michael.strauss@amd.com, Charlene.Liu@amd.com, David.Galiffi@amd.com, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH AUTOSEL 5.4 5/8] drm/amd/display: Fix pixel clock programming Date: Wed, 24 Aug 2022 21:39:24 -0400 Message-Id: <20220825013932.23467-5-sashal@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220825013932.23467-1-sashal@kernel.org> References: <20220825013932.23467-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ilya Bakoulin [ Upstream commit 04fb918bf421b299feaee1006e82921d7d381f18 ] [Why] Some pixel clock values could cause HDMI TMDS SSCPs to be misaligned between different HDMI lanes when using YCbCr420 10-bit pixel format. BIOS functions for transmitter/encoder control take pixel clock in kHz increments, whereas the function for setting the pixel clock is in 100Hz increments. Setting pixel clock to a value that is not on a kHz boundary will cause the issue. [How] Round pixel clock down to nearest kHz in 10/12-bpc cases. Reviewed-by: Aric Cyr Acked-by: Brian Chang Signed-off-by: Ilya Bakoulin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index eca67d5d5b10..721be82ccebe 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -546,9 +546,11 @@ static void dce112_get_pix_clk_dividers_helper ( switch (pix_clk_params->color_depth) { case COLOR_DEPTH_101010: actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 5) >> 2; + actual_pixel_clock_100hz -= actual_pixel_clock_100hz % 10; break; case COLOR_DEPTH_121212: actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 6) >> 2; + actual_pixel_clock_100hz -= actual_pixel_clock_100hz % 10; break; case COLOR_DEPTH_161616: actual_pixel_clock_100hz = actual_pixel_clock_100hz * 2; -- 2.35.1