Re: [PATCH net-next] net: phy: micrel: Adding SQI support for lan8814 phy

Andrew Lunn
2022-08-26T19:42:55Z

> > I just took a quick look at the datasheet. It says:
> >
>
> I'm not sure the datasheet you looked into is the right one. Could you please crosscheck if its lan8814 or lan8841.
> Lan8814 is quad port phy where register access are of extended page. Lan8841 is 1 port phy where register access are mmd access.
>
> > All registers references in this section are in MMD Device Address 1
> >
> > So you should be using phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
> > xxx) to read/write these registers. The datasheet i have however is missing
> > the register map, so i've no idea if it is still 0xe6.

https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/DS-LAN8814-00003592C.pdf

5.13.4 OPEN ALLIANCE TC1/TC12 DCQ SIGNAL QUALITY INDEX

Note: All registers references in this section are in MMD Device Address 1.

This section defines the implementation of section 6.1.2 of the TC1
and TC12 specifications. This mode builds upon the OPEN Alliance
TC1/TC12 DCQ Mean Square Error method by mapping the MSE value onto a
simple quality index. This mode is enabled by setting the sqi_enable
bit, in the DCQ Configuration register.

The MSE value is compared to the thresholds set in the DCQ SQI Table
Registers to provide an SQI value between 0 (worst value) and 7 (best
value) as follows:

In order to capture the SQI value, the DCQ Read Capture bit in the DCQ
Configuration register needs to be written as a high with the desired
cable pair specified in the DCQ Channel Number field of the same
register. The DCQ Read Capture bit will immediately self-clear and the
result will be available in the DCQ SQI register. In addition to the
current SQI, the worst case (lowest) SQI since the last read is
available in the SQI Worst Case field. The correlation between the
SQI values stored in the DCQ SQI register and an according Signal to
Noise Ratio (SNR) based on Additive White Gaussian (AWG) noise
(bandwidth of 80 MHz @ 100 Mbps / 550 MHz @ 1000 Mbps) is shown in
Table 5-5. The bit error rates to be expected in the case of white
noise as interference signal is shown in the table as well for
information purposes.

I had a quick look at OPEN ALLIANCE specification. It seems to specify
how each of these registers should look. It just failed to specify
where in the address map they are. So if you look at drivers
implementing SQI, you see most poke around in MDIO_MMD_VEND1. I
wounder if we can actually share the implementation between drivers,
those that follow the standard, with some paramatirisation where the
registers are.

Andrew