From: Adrian Hunter <adrian.hunter@intel.com>
To: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Jiri Olsa <jolsa@redhat.com>, Namhyung Kim <namhyung@kernel.org>,
Ian Rogers <irogers@google.com>, Andi Kleen <ak@linux.intel.com>,
linux-kernel@vger.kernel.org
Subject: [PATCH 3/5] perf intel-pt: Improve man page layout slightly
Date: Thu, 1 Sep 2022 14:00:30 +0300 [thread overview]
Message-ID: <20220901110032.9226-4-adrian.hunter@intel.com> (raw)
In-Reply-To: <20220901110032.9226-1-adrian.hunter@intel.com>
Improve man page layout slightly by adding blank lines.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
---
tools/perf/Documentation/perf-intel-pt.txt | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/tools/perf/Documentation/perf-intel-pt.txt b/tools/perf/Documentation/perf-intel-pt.txt
index 3dc3f0ccbd51..d5ddb968bcf4 100644
--- a/tools/perf/Documentation/perf-intel-pt.txt
+++ b/tools/perf/Documentation/perf-intel-pt.txt
@@ -943,12 +943,15 @@ event packets are recorded only if the "pwr_evt" config term was used. Refer to
the config terms section above. The power events record information about
C-state changes, whereas CBR is indicative of CPU frequency. perf script
"event,synth" fields display information like this:
+
cbr: cbr: 22 freq: 2189 MHz (200%)
mwait: hints: 0x60 extensions: 0x1
pwre: hw: 0 cstate: 2 sub-cstate: 0
exstop: ip: 1
pwrx: deepest cstate: 2 last cstate: 2 wake reason: 0x4
+
Where:
+
"cbr" includes the frequency and the percentage of maximum non-turbo
"mwait" shows mwait hints and extensions
"pwre" shows C-state transitions (to a C-state deeper than C0) and
@@ -956,6 +959,7 @@ Where:
"exstop" indicates execution stopped and whether the IP was recorded
exactly,
"pwrx" indicates return to C0
+
For more details refer to the Intel 64 and IA-32 Architectures Software
Developer Manuals.
@@ -969,8 +973,10 @@ are quite important. Users must know if what they are seeing is a complete
picture or not. The "e" option may be followed by flags which affect what errors
will or will not be reported. Each flag must be preceded by either '+' or '-'.
The flags supported by Intel PT are:
+
-o Suppress overflow errors
-l Suppress trace data lost errors
+
For example, for errors but not overflow or data lost errors:
--itrace=e-o-l
@@ -980,9 +986,11 @@ decoded packets and instructions. Note that this option slows down the decoder
and that the resulting file may be very large. The "d" option may be followed
by flags which affect what debug messages will or will not be logged. Each flag
must be preceded by either '+' or '-'. The flags support by Intel PT are:
+
-a Suppress logging of perf events
+a Log all perf events
+o Output to stdout instead of "intel_pt.log"
+
By default, logged perf events are filtered by any specified time ranges, but
flag +a overrides that.
--
2.25.1
next prev parent reply other threads:[~2022-09-01 11:01 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-01 11:00 [PATCH 0/5] perf intel-pt: Support itrace option flag d+e to log on error Adrian Hunter
2022-09-01 11:00 ` [PATCH 1/5] perf tools: Add perf_config_scan() Adrian Hunter
2022-09-01 11:00 ` [PATCH 2/5] perf auxtrace: Add itrace option flag d+e to log on error Adrian Hunter
2022-09-01 11:00 ` Adrian Hunter [this message]
2022-09-01 11:00 ` [PATCH 4/5] perf intel-pt: Improve object code read error message Adrian Hunter
2022-09-01 11:00 ` [PATCH 5/5] perf intel-pt: Support itrace option flag d+e to log on error Adrian Hunter
2022-09-01 14:31 ` Andi Kleen
2022-09-01 16:28 ` Adrian Hunter
2022-09-02 1:34 ` Namhyung Kim
2022-09-02 12:01 ` Adrian Hunter
2022-09-02 19:06 ` Arnaldo Carvalho de Melo
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