From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF98FECAAA1 for ; Tue, 6 Sep 2022 20:04:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230234AbiIFUEh (ORCPT ); Tue, 6 Sep 2022 16:04:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44034 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230036AbiIFUEC (ORCPT ); Tue, 6 Sep 2022 16:04:02 -0400 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B2211409B; Tue, 6 Sep 2022 12:59:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662494382; x=1694030382; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1GmuwRmBcP+qpqm868ZlLiTER6yT1AblOqnH4Dlpe/4=; b=WUlupqneHjKsRzvVz5N7pYtc/7DBPiirwHapJDv4QeFXpVRxepSnlse3 aFFUPEpdIzMt+UiIVhEWDVfQZu0HZZ5CBdiGcW2/N5UAiupHxDpRjg2EX EZZgA48SD+FpN2HUlA7eT4YyzOinivUqwNwrSiUX8D2zDSdhDJpPbtO4j Hn2gt2n8WOTV9w5/AR8QG8NenET3Z/xzZAo5utD4uMn329mZ/0iQJuVYQ ef4yJZQefP3YQJ/03Yz7aphJEBh+c/idTrJOQxExkTVIWjblteWJnioA3 obkP6IicAugRq2McUcevoIDKGcGrv1CkE1005rtaLuG+jLe1PlTsZkrYT Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10462"; a="358407370" X-IronPort-AV: E=Sophos;i="5.93,294,1654585200"; d="scan'208";a="358407370" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Sep 2022 12:57:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,294,1654585200"; d="scan'208";a="647351096" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga001.jf.intel.com with ESMTP; 06 Sep 2022 12:57:32 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id 4D24657F; Tue, 6 Sep 2022 22:57:46 +0300 (EEST) From: Andy Shevchenko To: Andy Shevchenko , linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org Cc: Thierry Reding , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Subject: [PATCH v1 9/9] pwm: lpss: Allow other drivers to enable PWM LPSS Date: Tue, 6 Sep 2022 22:57:35 +0300 Message-Id: <20220906195735.87361-9-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220906195735.87361-1-andriy.shevchenko@linux.intel.com> References: <20220906195735.87361-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The PWM LPSS device can be embedded in another device. In order to enable it, allow that drivers to probe a corresponding device. Signed-off-by: Andy Shevchenko --- drivers/pwm/pwm-lpss.h | 26 ++--------------- include/linux/platform_data/x86/pwm-lpss.h | 33 ++++++++++++++++++++++ 2 files changed, 35 insertions(+), 24 deletions(-) create mode 100644 include/linux/platform_data/x86/pwm-lpss.h diff --git a/drivers/pwm/pwm-lpss.h b/drivers/pwm/pwm-lpss.h index 35e570067fc6..41cb4b6246bb 100644 --- a/drivers/pwm/pwm-lpss.h +++ b/drivers/pwm/pwm-lpss.h @@ -13,11 +13,9 @@ #include #include -#define MAX_PWMS 4 - -struct device; +#include -struct pwm_lpss_boardinfo; +#define MAX_PWMS 4 struct pwm_lpss_chip { struct pwm_chip chip; @@ -25,23 +23,6 @@ struct pwm_lpss_chip { const struct pwm_lpss_boardinfo *info; }; -struct pwm_lpss_boardinfo { - unsigned long clk_rate; - unsigned int npwm; - unsigned long base_unit_bits; - /* - * Some versions of the IP may stuck in the state machine if enable - * bit is not set, and hence update bit will show busy status till - * the reset. For the rest it may be otherwise. - */ - bool bypass; - /* - * On some devices the _PS0/_PS3 AML code of the GPU (GFX0) device - * messes with the PWM0 controllers state, - */ - bool other_devices_aml_touches_pwm_regs; -}; - /* BayTrail */ static __maybe_unused const struct pwm_lpss_boardinfo pwm_lpss_byt_info = { .clk_rate = 25000000, @@ -72,7 +53,4 @@ static __maybe_unused const struct pwm_lpss_boardinfo pwm_lpss_tng_info = { .base_unit_bits = 22, }; -struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, void __iomem *base, - const struct pwm_lpss_boardinfo *info); - #endif /* __PWM_LPSS_H */ diff --git a/include/linux/platform_data/x86/pwm-lpss.h b/include/linux/platform_data/x86/pwm-lpss.h new file mode 100644 index 000000000000..296bd837ddbb --- /dev/null +++ b/include/linux/platform_data/x86/pwm-lpss.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Intel Low Power Subsystem PWM controller driver */ + +#ifndef __PLATFORM_DATA_X86_PWM_LPSS_H +#define __PLATFORM_DATA_X86_PWM_LPSS_H + +#include + +struct device; + +struct pwm_lpss_chip; + +struct pwm_lpss_boardinfo { + unsigned long clk_rate; + unsigned int npwm; + unsigned long base_unit_bits; + /* + * Some versions of the IP may stuck in the state machine if enable + * bit is not set, and hence update bit will show busy status till + * the reset. For the rest it may be otherwise. + */ + bool bypass; + /* + * On some devices the _PS0/_PS3 AML code of the GPU (GFX0) device + * messes with the PWM0 controllers state, + */ + bool other_devices_aml_touches_pwm_regs; +}; + +struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, void __iomem *base, + const struct pwm_lpss_boardinfo *info); + +#endif /* __PLATFORM_DATA_X86_PWM_LPSS_H */ -- 2.35.1