From: Jisheng Zhang <jszhang@kernel.org>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org
Subject: [PATCH v3 3/3] riscv: select HAVE_POSIX_CPU_TIMERS_TASK_WORK
Date: Mon, 26 Sep 2022 00:24:00 +0800 [thread overview]
Message-ID: <20220925162400.1606-4-jszhang@kernel.org> (raw)
In-Reply-To: <20220925162400.1606-1-jszhang@kernel.org>
Move POSIX CPU timer expiry and signal delivery into task context to
allow PREEMPT_RT setups to coexist with KVM.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
arch/riscv/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 79e52441e18b..7a8134fd7ec9 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -104,6 +104,7 @@ config RISCV
select HAVE_PERF_EVENTS
select HAVE_PERF_REGS
select HAVE_PERF_USER_STACK_DUMP
+ select HAVE_POSIX_CPU_TIMERS_TASK_WORK
select HAVE_REGS_AND_STACK_ACCESS_API
select HAVE_FUNCTION_ARG_ACCESS_API
select HAVE_STACKPROTECTOR
--
2.34.1
next prev parent reply other threads:[~2022-09-25 16:33 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-25 16:23 [PATCH v3 0/3] riscv: kvm: use generic entry for TIF_NOTIFY_RESUME and misc Jisheng Zhang
2022-09-25 16:23 ` [PATCH v3 1/3] RISC-V: KVM: Record number of signal exits as a vCPU stat Jisheng Zhang
2022-09-28 5:18 ` Guo Ren
2022-09-28 8:59 ` Andrew Jones
2022-09-25 16:23 ` [PATCH v3 2/3] RISC-V: KVM: Use generic guest entry infrastructure Jisheng Zhang
2022-09-25 16:24 ` Jisheng Zhang [this message]
2022-09-28 9:00 ` [PATCH v3 0/3] riscv: kvm: use generic entry for TIF_NOTIFY_RESUME and misc Andrew Jones
2022-10-01 12:37 ` Anup Patel
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