From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3DEBC07E9D for ; Tue, 27 Sep 2022 14:50:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229810AbiI0OuE (ORCPT ); Tue, 27 Sep 2022 10:50:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47944 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233032AbiI0Ot0 (ORCPT ); Tue, 27 Sep 2022 10:49:26 -0400 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D84EA4AD59; Tue, 27 Sep 2022 07:47:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1664290033; x=1695826033; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=A9XwjcYhm5i/e8vIjenDrCHIcT6qFMQ1yXOriuZ1ixc=; b=jjrHi7LFzrlsJAp9U9RI5LPpJcRVT4+mNZ0ND1dW83klxeBDQQbhvfwi KfAtoKOigWNm5BfLjrZDz6CltfzwkO7L1wXaw6daZcCAEBn/BcxOA8Oj5 XSW4G92mF3ueGy+M0+K7zNZNK341gs0moto51YcDrkQGJyEg9QaPGDvS4 kjh8gsiuO8hTolyiLzH17ObyXnu+P7y+PEbfpRmNRuP18a+0ZEEBzsmcK 4/asxqV7WePwj7ob7oyX99LmjJ+KT/O2rsMAyxA+YNaiKVgyBXOxPzhYm Gil3pVbqs1jsv5BLsAjfOuzkliV5viL+6RAgKVmiCYLrT6FNcL1wYO4fK A==; X-IronPort-AV: E=McAfee;i="6500,9779,10483"; a="363173002" X-IronPort-AV: E=Sophos;i="5.93,349,1654585200"; d="scan'208";a="363173002" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Sep 2022 07:47:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10483"; a="621544887" X-IronPort-AV: E=Sophos;i="5.93,349,1654585200"; d="scan'208";a="621544887" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga002.jf.intel.com with ESMTP; 27 Sep 2022 07:47:11 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id C5F26268; Tue, 27 Sep 2022 17:47:27 +0300 (EEST) From: Andy Shevchenko To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Hans de Goede , Andy Shevchenko , linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Thierry Reding Subject: [PATCH v3 7/8] pwm: lpss: Make use of bits.h macros for all masks Date: Tue, 27 Sep 2022 17:47:22 +0300 Message-Id: <20220927144723.9655-8-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220927144723.9655-1-andriy.shevchenko@linux.intel.com> References: <20220927144723.9655-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Make use of the GENMASK() (far less error-prone, far more concise). Signed-off-by: Andy Shevchenko Reviewed-by: Hans de Goede Acked-by: Uwe Kleine-König --- drivers/pwm/pwm-lpss.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c index a20915459809..accdef5dd58e 100644 --- a/drivers/pwm/pwm-lpss.c +++ b/drivers/pwm/pwm-lpss.c @@ -10,6 +10,7 @@ * Author: Alan Cox */ +#include #include #include #include @@ -26,7 +27,7 @@ #define PWM_ENABLE BIT(31) #define PWM_SW_UPDATE BIT(30) #define PWM_BASE_UNIT_SHIFT 8 -#define PWM_ON_TIME_DIV_MASK 0x000000ff +#define PWM_ON_TIME_DIV_MASK GENMASK(7, 0) /* Size of each PWM register space if multiple */ #define PWM_SIZE 0x400 -- 2.35.1