From: Stephen Boyd <sboyd@kernel.org>
To: Rahul Tanwar <rtanwar@maxlinear.com>,
linux-clk@vger.kernel.org, mturquette@baylibre.com
Cc: linux-kernel@vger.kernel.org, linux-lgm-soc@maxlinear.com,
Rahul Tanwar <rtanwar@maxlinear.com>
Subject: Re: [PATCH RESEND v2 1/5] clk: mxl: Switch from direct readl/writel based IO to regmap based IO
Date: Wed, 28 Sep 2022 17:14:13 -0700 [thread overview]
Message-ID: <20220929001416.6F090C433D6@smtp.kernel.org> (raw)
In-Reply-To: <4c56443ecd9041f102681ebf36b6854090ab82e3.1663827071.git.rtanwar@maxlinear.com>
Quoting Rahul Tanwar (2022-09-21 23:24:24)
> diff --git a/drivers/clk/x86/clk-cgu-pll.c b/drivers/clk/x86/clk-cgu-pll.c
> index 3179557b5f78..c83083affe88 100644
> --- a/drivers/clk/x86/clk-cgu-pll.c
> +++ b/drivers/clk/x86/clk-cgu-pll.c
> @@ -1,8 +1,9 @@
> // SPDX-License-Identifier: GPL-2.0
> /*
> + * Copyright (C) 2020-2022 MaxLinear, Inc.
> * Copyright (C) 2020 Intel Corporation.
> - * Zhu YiXin <yixin.zhu@intel.com>
> - * Rahul Tanwar <rahul.tanwar@intel.com>
> + * Zhu Yixin <yzhu@maxlinear.com>
Does Zhu Yixin approve? They're not Cced on this patch.
> + * Rahul Tanwar <rtanwar@maxlinear.com>
> */
>
> #include <linux/clk-provider.h>
next prev parent reply other threads:[~2022-09-29 0:14 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-22 6:24 [PATCH RESEND v2 0/5] Modify MxL's CGU clk driver to make it secure boot compatible Rahul Tanwar
2022-09-22 6:24 ` [PATCH RESEND v2 1/5] clk: mxl: Switch from direct readl/writel based IO to regmap based IO Rahul Tanwar
2022-09-29 0:14 ` Stephen Boyd [this message]
2022-09-29 5:29 ` Rahul Tanwar
2022-09-22 6:24 ` [PATCH RESEND v2 2/5] clk: mxl: Remove unnecessary spinlocks Rahul Tanwar
2022-09-29 0:16 ` Stephen Boyd
2022-09-29 5:37 ` Rahul Tanwar
2022-09-22 6:24 ` [PATCH RESEND v2 3/5] clk: mxl: Avoid disabling gate clocks from clk driver Rahul Tanwar
2022-09-29 0:17 ` Stephen Boyd
2022-09-29 5:45 ` Rahul Tanwar
[not found] ` <20220930010123.38984C4347C@smtp.kernel.org>
2022-10-05 10:52 ` Rahul Tanwar
[not found] ` <MN2PR19MB369301BFE8DFB56C348CD6C0B15D9@MN2PR19MB3693.namprd19.prod.outlook.com>
[not found] ` <20221005202037.E7B43C433C1@smtp.kernel.org>
2022-10-11 7:33 ` Rahul Tanwar
2022-09-22 6:24 ` [PATCH RESEND v2 4/5] clk: mxl: Add validation for register reads/writes Rahul Tanwar
2022-09-29 0:20 ` Stephen Boyd
2022-09-29 6:10 ` Rahul Tanwar
[not found] ` <20220930010212.7860DC433C1@smtp.kernel.org>
2022-10-05 10:52 ` Rahul Tanwar
2022-09-22 6:24 ` [PATCH RESEND v2 5/5] clk: mxl: Add a missing flag to allow parent clock rate change Rahul Tanwar
2022-09-29 0:18 ` Stephen Boyd
2022-09-29 5:46 ` Rahul Tanwar
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