From: Stephen Boyd <sboyd@kernel.org>
To: Rahul Tanwar <rtanwar@maxlinear.com>,
linux-clk@vger.kernel.org, mturquette@baylibre.com
Cc: linux-kernel@vger.kernel.org, linux-lgm-soc@maxlinear.com,
Rahul Tanwar <rtanwar@maxlinear.com>
Subject: Re: [PATCH RESEND v2 3/5] clk: mxl: Avoid disabling gate clocks from clk driver
Date: Wed, 28 Sep 2022 17:17:40 -0700 [thread overview]
Message-ID: <20220929001745.A4F9FC433B5@smtp.kernel.org> (raw)
In-Reply-To: <5a88bd5a9e93cc6e794080e5cac821ae0c27ec56.1663827071.git.rtanwar@maxlinear.com>
Quoting Rahul Tanwar (2022-09-21 23:24:26)
> In MxL's LGM SoC, gate clocks are supposed to be enabled or disabled
> from EPU (power management IP) in certain power saving modes. If gate
> clocks are allowed to be enabled/disabled from CGU clk driver, then
> there arises a conflict where in case clk driver disables a gate clk,
> and then EPU tries to disable the same gate clk, then it will hang
> polling for the clk gated successful status.
Is there any point in registering these clks when they're not supposed
to be controlled from Linux?
next prev parent reply other threads:[~2022-09-29 0:17 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-22 6:24 [PATCH RESEND v2 0/5] Modify MxL's CGU clk driver to make it secure boot compatible Rahul Tanwar
2022-09-22 6:24 ` [PATCH RESEND v2 1/5] clk: mxl: Switch from direct readl/writel based IO to regmap based IO Rahul Tanwar
2022-09-29 0:14 ` Stephen Boyd
2022-09-29 5:29 ` Rahul Tanwar
2022-09-22 6:24 ` [PATCH RESEND v2 2/5] clk: mxl: Remove unnecessary spinlocks Rahul Tanwar
2022-09-29 0:16 ` Stephen Boyd
2022-09-29 5:37 ` Rahul Tanwar
2022-09-22 6:24 ` [PATCH RESEND v2 3/5] clk: mxl: Avoid disabling gate clocks from clk driver Rahul Tanwar
2022-09-29 0:17 ` Stephen Boyd [this message]
2022-09-29 5:45 ` Rahul Tanwar
[not found] ` <20220930010123.38984C4347C@smtp.kernel.org>
2022-10-05 10:52 ` Rahul Tanwar
[not found] ` <MN2PR19MB369301BFE8DFB56C348CD6C0B15D9@MN2PR19MB3693.namprd19.prod.outlook.com>
[not found] ` <20221005202037.E7B43C433C1@smtp.kernel.org>
2022-10-11 7:33 ` Rahul Tanwar
2022-09-22 6:24 ` [PATCH RESEND v2 4/5] clk: mxl: Add validation for register reads/writes Rahul Tanwar
2022-09-29 0:20 ` Stephen Boyd
2022-09-29 6:10 ` Rahul Tanwar
[not found] ` <20220930010212.7860DC433C1@smtp.kernel.org>
2022-10-05 10:52 ` Rahul Tanwar
2022-09-22 6:24 ` [PATCH RESEND v2 5/5] clk: mxl: Add a missing flag to allow parent clock rate change Rahul Tanwar
2022-09-29 0:18 ` Stephen Boyd
2022-09-29 5:46 ` Rahul Tanwar
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