Re: [PATCH RESEND v2 4/5] clk: mxl: Add validation for register reads/writes

[Stephen Boyd <sboyd@kernel.org>]

Quoting Rahul Tanwar (2022-09-21 23:24:27)
> Some clocks support parent clock dividers but they do not
> support clock gating (clk enable/disable). Such types of
> clocks might call API's for get/set_reg_val routines with
> width as 0 during clk_prepare_enable() call. Handle such
> cases by first validating width during clk_prepare_enable()
> while still supporting clk_set_rate() correctly.
> 
> Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com>
> ---
>  drivers/clk/x86/clk-cgu.h | 30 ++++++++++++++++++++++++++----
>  1 file changed, 26 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/clk/x86/clk-cgu.h b/drivers/clk/x86/clk-cgu.h
> index 73ce84345f81..46daf9ebd6c9 100644
> --- a/drivers/clk/x86/clk-cgu.h
> +++ b/drivers/clk/x86/clk-cgu.h
> @@ -299,29 +299,51 @@ struct lgm_clk_branch {
>  static inline void lgm_set_clk_val(struct regmap *membase, u32 reg,
>                                    u8 shift, u8 width, u32 set_val)
>  {
> -       u32 mask = (GENMASK(width - 1, 0) << shift);
> +       u32 mask;
>  
> +       /*
> +        * Some clocks support parent clock dividers but they do not
> +        * support clock gating (clk enable/disable). Such types of
> +        * clocks might call this function with width as 0 during
> +        * clk_prepare_enable() call. Handle such cases by not doing
> +        * anything during clk_prepare_enable() but handle clk_set_rate()
> +        * correctly
> +        */
> +       if (!width)
> +               return;

Why are the clk_ops assigned in a way that makes the code get here? Why
can't we have different clk_ops, or not register the clks at all, when
the hardware can't be written?

> +
> +       mask = (GENMASK(width - 1, 0) << shift);
>         regmap_update_bits(membase, reg, mask, set_val << shift);