From: Stephen Boyd <sboyd@kernel.org>
To: Sean Anderson <seanga2@gmail.com>,
linux-clk@vger.kernel.org, linux-mips@vger.kernel.org
Cc: Yang Ling <gnaygnil@gmail.com>,
linux-kernel@vger.kernel.org,
Kelvin Cheung <keguang.zhang@gmail.com>,
Stephen Boyd <sboyd@codeaurora.org>,
Du Huanpeng <dhu@hodcarrier.org>,
Sean Anderson <seanga2@gmail.com>
Subject: Re: [RESEND PATCH] clk: ls1c: Fix PLL rate calculation
Date: Mon, 17 Oct 2022 14:09:47 -0700 [thread overview]
Message-ID: <20221017210949.1B54AC433D6@smtp.kernel.org> (raw)
In-Reply-To: <20220823033414.198525-1-seanga2@gmail.com>
Quoting Sean Anderson (2022-08-22 20:34:14)
> While reviewing Dhu's patch adding ls1c300 clock support to U-Boot [1], I
> noticed the following calculation, which is copied from
> drivers/clk/loongson1/clk-loongson1c.c:
>
Nobody has provided a review for this patch. If it is still important,
please resend. Thanks.
prev parent reply other threads:[~2022-10-17 21:10 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-23 3:34 [RESEND PATCH] clk: ls1c: Fix PLL rate calculation Sean Anderson
2022-08-23 3:35 ` Sean Anderson
2022-08-24 1:28 ` Du Huanpeng
2022-10-17 21:09 ` Stephen Boyd [this message]
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